Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal

This schematic, which has already been considered in previous tutorials will be used to illustrate various simulation modes The block fsm_data will be verified with the aid of different simulation techniques 1 means YES S 0...S 7 Data can be entered from DIP switchers and the result can be displayed on LCD. Thus, the circuit can be not only verified in simulator but can also be tested in FPGA

This block permits to check if an 8-bit vector has 3 or more successive ones 1 0 S 0...S = x”A7” contains 3 successive ones 1 means YES 1 it means YES it contains at least 3 successive ones library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsm_data is Port ( rin : in std_logic_vector(7 downto 0); result : out std_logic_vector(3 downto 0); reset : in std_logic; clk : in std_logic); end fsm_data; Just one less-significant bit of the result is used. This was done to avoid changes in the remaining circuit that is also used for other examples that require all 4 bits of the result 0-NO 1-YES

architecture Behavioral of fsm_data is type STATE_TYPE is (start, one_one, two_ones, three_ones); signal CS, NS: STATE_TYPE; signal tmp : std_logic; signal index : integer range 0 to 8; begin process (clk,reset) begin if reset='1' then CS <= start; elsif (clk'event and clk = '1') then CS <= NS; end if; end process; Current State of FSM Next State of FSM 1 0 S 0...S 7 extra index temporary value for the result (either 1 – YES or 0 - NO)

process (CS,rin,index) begin if index = 8 then NS <= start; else case CS is when start => tmp <= '0'; if (rin(index) = '1') then NS <= one_one; else NS <= start; end if; when one_one => if (rin(index) = '1') then NS <= two_ones; else NS <= start; end if; when two_ones => if (rin(index) = '1') then NS <= three_ones; else NS <= start; end if; when three_ones => tmp <= '1'; if index = 0 then NS <= start; else NS <= three_ones; end if; end case; end if; end process; one_one two_ones start index = 0, i.e. start from the beginning three_ones There are 3 successive ones

process (clk,reset) begin if (reset='1') then index <= 0; result '0'); elsif falling_edge(clk) then if index = 7 then result <= "000" & tmp; end if; if index = 8 then index <= 0; else index <= index+1; end if; end process; end Behavioral; 1 0 S 0...S storing the result skipping one clock cycle for resynchronization between FSM and process (rising edge) end this process (falling edge) Just the less significant bit might be changed

right mouse button click right mouse button click

19 Set 1 and 0 with the aid of mouse (click left mouse button) left mouse button double click 9D 16 =

1 2 left mouse button double click 3

period The Input setup time defines when inputs must be valid The Output valid delay defines the time after active clock edge when the outputs must be valid

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(3 downto 0); index_out: out std_logic_vector(3 downto 0)); end VHDL_test; architecture Behavioral of VHDL_test is function parity (input : std_logic_vector)return std_logic is variable temp : std_logic := '0'; begin for i in input'range loop temp := temp xor input(i); end loop; return temp; end parity; begin data_out <= "000" & parity(data_in); end Behavioral;

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4 Workspace 1 325

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity shift_r is Port ( CLK: in STD_LOGIC; RESET : in STD_LOGIC; DIN: in STD_LOGIC; DOUT: out STD_LOGIC_VECTOR(3 downto 0)); end shift_r; architecture Behavioral of shift_r is signal REG: STD_LOGIC_VECTOR(3 downto 0); begin process (CLK,RESET) begin if reset = '1' then REG '0'); elsif CLK'event and CLK='1' then REG <= DIN & REG(3 downto 1); end if; DOUT <= REG; end process; end Behavioral; BIT2BIT3BIT1BIT0 CLK RESET DIN DOUT

6 7 8 right mouse button click 9 the compiled design unit 10 left mouse button double click

15 left mouse button double click 16 17

Run Restart Run Continue Run Run All Break

see slides 2-6 This can be done just in ModelSim environment, i.e. without Xilinx ISE 5.x

Double click left mouse button to load the design

Main Window Workspace Transcript (command line) Dataflow window The Dataflow window allows to explore the "physical" connectivity of the design. It displays processes and signals, nets, and registers. Process window displays a list of processes Signals window The left pane shows the names of HDL items. The left pane shows the values of the associated HDL items at the end of the current run Source window The Source window allows to view and edit HDL source code Variables window Wave window allows to view the results of simulation.

force clk 0 0, repeat force reset 1 0, force rin rin = clk reset

The value of rin specified in the file stimulus current state (CS)next state (NS) After one iteration (index is changed from 0 to 8) the result is equal to 1 (YES) reset clock tmp keeps intermediate result

left mouse button click break can be set only for blue numbers click left mouse button to disable (to enable break point)

To delete the breakpoint or to change its options, click the line number with the right mouse button 43 breakpoint step 44 Step inserting a cursor deleting a cursor

The first cursor The second cursor Time between the cursors Point to a wave with the mouse in order to see the value Point to a wave with the mouse in order to see the value find previous transition find next transition

Zoom with mouse specifying zoom area

to quit simulation to quit ModelSim

list window shows all changes of signals step by step You can use list window much like wave window this vector contains 5 values “1” compare this two pictures