Company LOGO Final presentation Spring 2008/9 Performed by: Alexander PavlovDavid Domb Supervisor: Mony Orbach GPS/INS Computing System

Agenda 1. General overview 2. Our Project 4. Results GPS/INS Computing System 3. The Design 5. Summary

GPS/INS Computing System General overview “Even Noah got no salary for the first six months partly on account of the weather and partly because he was learning navigation.” Mark Twain

Theoretical Navigation Algorithm 0 Initialization 1 Particle Propagation 2 Particle Update & Normalization 3 State Estimation 4 Effective N calculation 5 D computation 6 Re-sampling 7 Regularization 8 Weight Re-computation GPS/INS Computing System  Developed in the “Technion” and Implements the tightly coupled INS/GPS navigation unit, with the particle filter.  The algorithm stages:

Project Goals Establishing the efficiency of the particle filter based, tightly coupled INS/GPS navigation unit realization. Designing an efficient real- time particle filter based, tightly coupled INS/GPS navigation unit. GPS/INS Computing System

GPS Computing System

General Our goal was to implement Particle Propagation and State Estimation stages. Both stages are required to function within 0.01 sec. GPS Computing System

Group Project Goals – Part 1 Designing in FPGA environment Implementation of Particle Propagation and State Estimation stages of algorithm GPS/INS Computing System

Solution – Top design GPS/INS Computing System Weight vector Particles propagation unit State estimation unit Estimated State Vector [1..18] Estimated State Vector [1..18] xN Extended State Vector [1..18] Extended State Vector [1..18] Extended State Vector [1..18] Controller

Basic architecture 24Bit words data bus. FIFO-Like streaming interfaces ( Request + Empty / Full ) Controlled By Start/Finished activation mechanism Basic Streaming Block Basic Streaming Block Start Finished Control Input Path Output Path

Particle propagation unit GPS/INS Computing System clock reset start finish Particle Propagation Unit X[0..439] INS[0..287] X_OUT[0..439]

Particle propagation unit GPS/INS Computing System Propagation Unit 1 Propagation Unit 2 Propagation Unit 6 MUX (6 to 1) Propagation timing control

Single particle propagation data flow Format inputs to 48 bits Calculate trigonometric functions Latitude sin/cos Format trigonometric function output to 48 bits R_E, R_e, R_N calculation Denominator calculation d_longitude denominator d_latitude denominator Dividers d_longitude d_lattitude R_e Particle Propagation GPS Computing System Propagation flow control

Estimation unit GPS/INS Computing System clock reset New_Data_In Estimation_Ready Estimation Unit X[0..439] W[0..23] ESTIMATED_DATA [0..439]

Estimation unit GPS/INS Computing System W X Σ Estimated Data ×

GPS Computing System

Timing Analysis GPS/INS Computing System  1 particle Propagation LATENCY – 50 clock cycles (from “start” to “finish”) of propagation and weighting (according to simulation).  With a pipeline (Throughput) of 8 clocks, and 6 parallel propagation units : 30,000 particles in 240,040 clocks = ~ 8 30Mhz.

GPS Computing System Timing Analysis Finish time for particles: Latency & Throughput:

Resources Analysis GPS/INS Computing System  According to the compilation report, only 60% of the FPGA logic element are utilized.

COMMENTS GPS/INS Computing System  NO sin/cos blocks: the design uses a “DUMMY” block with a latency of 30 clocks and no throughput.  The estimation of the quaternion matrix is left to be resolved by another grope (by software). The matrix is part of the design’s output.  The design is based on the original “bits per field” distribute.

GPS Computing System

Group’s goals achievement GPS/INS Computing System Learning GPS/INS navigation using Particle Filter algorithm Learning VHDL language Learning FPGA environment Implementation of Particle Propagation and State Estimation stages of algorithm

Project Goals GPS/INS Computing System We have Established that it is possible to implement the “Propagation” and “Estimation” stages of the project, within the necessary timing requirements. According to FPGA logic utilization and timing results, we can see that there is a lot of “growth capability” (faster results and more accuracy).