Online Muon Capture and Decay Experiment Megan Alexander, Daniel Miner, Wojtek Skulski, Frank Wolfs University of Rochester Work funded by a grant from.

Slides:



Advertisements
Similar presentations
Laboratory for SoC design TEMPUS meeting Niš,
Advertisements

Kuno-Group B4 Yuuki Matsumoto A report for Graduation research Development of Trigger Board for MPPC (for MuSIC experiment) A report for Graduation research.
Introduction to QuarkNet Lab Summer 2012 R. Mountain, M. Soderberg, S. Blusk with Erika Cowan, Anna Fadeeva, Dylan Hsu, Emily Kraus.
Signal Digitization Issues for the NLC Muon Detector Mani Tripathi UC, Davis 8/5/03 Starting Point: 1.Time of arrival measurement with O(1 ns) resolution.
DAQ System to Search for GRBs using Water Cerenkov Detectors Mario Castillo*, Gonzalo Perez*, Humberto Salazar* and L. Villaseñor ** * Facultad de Ciencias.
STARLight PDR 3 Oct ‘01I.1 Miller STARLight Control Module Design Ryan Miller STARLight Electrical Engineer (734)
Muon Decay Experiment John Klumpp And Ainsley Niemkiewicz.
DSP online algorithms for the ATLAS TileCal Read Out Drivers Cristobal Cuenca Almenar IFIC (University of Valencia-CSIC)
Wojtek Skulski CERN Oberon Day March /2004 Experiment control and data acquisition using BlackBox Component Builder Wojtek Skulski Department of Physics.
Analog-to-Digital Converters
Frank L. H. WolfsDepartment of Physics and Astronomy, University of Rochester Using Digital Signal Processing in the Advanced Laboratory F. Wolfs, M. Alexander,
Aztec PC Scope Preliminary Design Review Fall 2006 Michael MasonJed Brown Andrew YoungsJosh Price.
S. Zuberi, University of Rochester Digital Signal Processing of Scintillator Pulses Saba Zuberi, Wojtek Skulski, Frank Wolfs University of Rochester.
Frank L. H. WolfsDepartment of Physics and Astronomy, University of Rochester The History of the Measurement of the Muon Lifetime. F. L. H. Wolfs Department.
Aztec PC Oscilloscope Michael Mason Jed Brown Josh Price Andrew Youngs.
Implementation of DSP Algorithm on SoC. Characterization presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompany engineer : Emilia Burlak.
Using FPGAs with Embedded Processors for Complete Hardware and Software Systems Jonah Weber May 2, 2006.
FPGA-Based Systems Design Flow in Action By: Ramtin Raji Kermani.
Summer Research Progress: Week 2 – DSP vs FPGA
® ChipScope ILA TM Xilinx and Agilent Technologies.
Xilinx at Work in Hot New Technologies ® Spartan-II 64- and 32-bit PCI Solutions Below ASSP Prices January
W.Skulski Phobos Workshop April /2003 Firmware & software development Digital Pulse Processor DDC-8 (Universal Trigger Module) Wojtek Skulski University.
NetBurner MOD 5282 Network Development Kit MCF 5282 Integrated ColdFire 32 bit Microcontoller 2 DB-9 connectors for serial I/O supports: RS-232, RS-485,
A Company Selling Technology and not just a Product.
Reconfigurable Communication System Design
SOC Consortium Course Material ASIC Logic National Taiwan University Adopted from National Chiao-Tung University IP Core Design.
BepiColombo/MMO/PWI/SORBET PWI meeting - Kanazawa 24/03/2006M.Dekkali MMO PWI Meeting Kanazawa University 24 th March 2006.
1 S. E. Tzamarias Hellenic Open University N eutrino E xtended S ubmarine T elescope with O ceanographic R esearch Readout Electronics DAQ & Calibration.
Digital Radio Receiver Amit Mane System Engineer.
Part A Presentation High Speed Digital Signal Lab Students: Lotem Sharon Yuval Sela Instructor : Ina Rivkin.
Status Report Atsushi Nukariya. FPGA training course ・ I solved 15 problems which are proposed by Uchida-san. ・ I used above circuit board. FPGA.
DLS Digital Controller Tony Dobbing Head of Power Supplies Group.
Low Cost Radar and Sonar using Open Source Hardware and Software
Font 4 Review Digital Feedback System BPM Analogue Processor Digital Processor Feather Kicker Power Amplifier Pick up StriplinesKicker StriplinesBeam.
K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 1 Development of fast electronics for the GRAPES-3 experiment at Ooty K.C. RAVINDRAN On Behalf of GRAPES-3 Collaboration.
FPGA (Field Programmable Gate Array): CLBs, Slices, and LUTs Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side.
Ethernet Based Embedded IOC for FEL Control Systems J. Yan, D. Sexton, Al Grippo, W. Moore, and K. Jordan ICALEPCS 2007 October 19, 2007 Knoxville Convention.
Commissioning of ICAL prototype detector electronics B.Satyanarayana TIFR, Mumbai.
A Front End and Readout System for PET Overview: –Requirements –Block Diagram –Details William W. Moses Lawrence Berkeley National Laboratory Department.
Electronics and data acquisition system of the extensive air shower detector array at the University of Puebla R. Conde 1, O. Martinez 1, T. Murrieta 1,
Measurement of lifetime for muons captured inside nuclei
Preliminary Design of FONT4 Digital ILC Feedback System Hamid Dabiri khah Queen Mary, University of London 30/05/2005.
Final Presentation Final Presentation OFDM implementation and performance test Performed by: Tomer Ben Oz Ariel Shleifer Guided by: Mony Orbach Duration:
W.Skulski APS April/2003 Eight-Channel Digital Pulse Processor And Universal Trigger Module. Wojtek Skulski, Frank Wolfs University of Rochester.
Algorithms for the ROD DSP of the ATLAS Hadronic Tile Calorimeter
Alexei SemenovGeneric Digitizer Generic Digitizer 10MHZ 16 bit 6U VME Board.
Fast Fault Finder A Machine Protection Component.
FPL Sept. 2, 2003 Software Decelerators Eric Keller, Gordon Brebner and Phil James-Roxby Xilinx Research Labs.
W.Skulski Phobos Workshop April /2003 Digital Pulse Processor DDC-8 (Universal Trigger Module) for PHOBOS. Wojtek Skulski University of Rochester.
SP04 Production Lev Uvarov RICE Muon Trigger Meeting August 27, 2004.
Mid-Term Presentation October 5, Team Members Charlie Mraz EE Team Leader Analog Design PCB Layout Allen Joiner EE Microprocessor Design Power Supply.
Group 10 – Extensible Digital Logic Educational Tool.
Capture and record 1GHz signal (Block Diagram)
Teaching Digital Logic courses with Altera Technology
Lab Environment and Miniproject Assignment Spring 2009 ECE554 Digital Engineering Laboratory.
FONT4 Status Report Glenn Christian John Adams Institute, Oxford for FONT collaboration.
Glen White, SLAC Jan th ATF2 Project Meeting, KEK
Low Cost Radar and Sonar using Open Source Hardware and Software
Using Xilinx ChipScope Pro Tools
“Performance test of a lead glass
Commissioning the SIS3316 Digitizer
ARM Cortex-M4 Combines DSP and microcontroller features
A First Look J. Pilcher 12-Mar-2004
Embedded Units In more complex FPGAs There are many specialized circuitry, particularly for DSP. These include a variety of Adders, Multipliers, Processors.
Neurochip3.
Speaker: Tian-Sheuan Chang July, 2004
The New Readout Electronics for the SLAC Focusing DIRC Prototype (SLAC experiment T-492 ) L. L. Ruckman, G. S. Varner Instrumentation Development Laboratory.
CSCI1600: Embedded and Real Time Software
CSCI1600: Embedded and Real Time Software
Command and Data Handling
Presentation transcript:

Online Muon Capture and Decay Experiment Megan Alexander, Daniel Miner, Wojtek Skulski, Frank Wolfs University of Rochester Work funded by a grant from the APS WYP 2005 and a grant from the NSF.

APS Meeting March 2006 M.Alexander 2 Overview Purpose: To capture and share data from cosmic muons, making a “real” physics experiment accessible to the public. In this talk: Experimental details Website tour

APS Meeting March 2006 M.Alexander 3 Motivation Time dilation (special relativity) Classic experiment, popular in advanced physics labs Outreach Mount Washington, NH

APS Meeting March 2006 M.Alexander 4 Detector (Scintillator + PMT) Experiment Setup Internet DDC-8 Circuit Board (DSP) Cosmic Muons Tools Xilinx Cypress EZ-USB BlackBox Apache XML/SWF Charts AWStats

APS Meeting March 2006 M.Alexander 5 DDC-8 Developed by Wojtek Skulski. Diagnostic OUT 40 MHz * 10 bits JTAG connector FPGA ADC 40 MHz * 10 bits (8 channels) 16 bidirectional TTL lines + 1 in (pool of extra logic I/O) Analog signal IN 8 channels (only 1 used) with digital offset and gain control RS-232 Logic connectors NIM 16 lines IN, 8 lines OUT USB RAM 500 kB ECL clock IN (optional) micro processor

APS Meeting March 2006 M.Alexander 6 Typical Muon Signals Stopping Muons: Passing Muons: μ+μ+ μ+μ+ e+e+ μ+μ+ veve μ+μ+ vμvμ

APS Meeting March 2006 M.Alexander 7 Web View: Waveforms Time constant: 2.1 μ s

APS Meeting March 2006 M.Alexander 8 Web View:Energy Spectra Conventional muon lifetime experiments do not exploit DSP for particle ID: this one does!

APS Meeting March 2006 M.Alexander 9 Downloadable Data

APS Meeting March 2006 M.Alexander 10 Downloadable Data View from Excel, MATLAB

APS Meeting March 2006 M.Alexander 11 Summary and Conclusion Physics outreach enabled by hardware, software, web tools. Total unique visitors: