Comunicación Serie

Bit Rate Vs Baud Rate Bit Rate= Bits/Seg BaudRate= Numero de Cambios en la señal /seg O Símbolos /seg Símbolo = Uno de los diferentes valores en la tensión frecuencia o Fase 2 Símbolos ( 0 y 1) que representan 2 valores distintos de tensión (1 bit /simbolo) Bit Rate =Baudrate 4 bit / Símbolo

OPEN SDA INTERFACE Open SDA K64F PC CDC Comunication Device Class UART1 RXD TXD RXD – PTB16 USB Open SDA UART0 K64F TXD – PTB17 PC USB Application Layer -Terminal -KDS (Kinetis Design Studio) USB-CDC Driver COM Port CDC Comunication Device Class Emulation of a Virtual Com Port using ACM (Abstract Control Model) subclass of CDC (on Linux Based computers /dev/ttyACM0)

UART Clock Gating Antes de usar un modulo se debe habilitar el clock de lo contrario se genera un error. De igual forma antes de apagar un clock se deberá deshabilitar el modulo. SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; SIM_SCGC4 |= SIM_SCGC4_UART1_MASK; SIM_SCGC4 |= SIM_SCGC4_UART2_MASK; SIM_SCGC4 |= SIM_SCGC4_UART3_MASK; SIM_SCGC1 |= SIM_SCGC1_UART4_MASK; SIM_SCGC1 |= SIM_SCGC1_UART5_MASK; En MK64F12.h #define SIM_SCGC4_UART0_MASK 0x400u #define SIM_SCGC4_UART1_MASK 0x800u #define SIM_SCGC4_UART2_MASK 0x1000u #define SIM_SCGC4_UART3_MASK 0x2000u #define SIM_SCGC1_UART4_MASK 0x400u #define SIM_SCGC1_UART5_MASK 0x800u

Baudrate Baud Rate Fractional Divisor (BRFD)= K/32 K=0…31 K=Baud Rate Fine Adjust (BRFA)

Baudrate 1- De [1] 2- De [1]

UART Clock Gating

UART0 PINS SETUP PCRstr UserPCR; UserPCR.PCR=false; UserPCR.FIELD.MUX=PORT_mAlt3; // UART0 UserPCR.FIELD.IRQC=PORT_eDisabled; // No Irq’s from port //Setup Tx and Rx pins PORT_Configure2(PORT_UART0,UART0_TX_PIN,UserPCR); PORT_Configure2(PORT_UART0,UART0_RX_PIN,UserPCR);

UART Definiciones MK64F12.h /** UART - Register Layout Typedef */ typedef struct { __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ uint8_t RESERVED_0[1]; __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ uint8_t RESERVED_1[1]; __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ union { /* offset: 0x1B */ __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ }; __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ } UART_Type, *UART_MemMapPtr;

UART Definiciones MK64F12.h #define UART0_BASE (0x4006A000u) /** Peripheral UART0 base pointer */ #define UART0 ((UART_Type *)UART0_BASE) #define UART0_BASE_PTR (UART0) Uso: UART0 -> C2= Some Value;

UART Registros Mas comunes TE : Habilita Transmisor RE : Habilita Receptor Ejemplo: UART0->C2=UART_C2_TE_MASK | UART_C2_RE_MASK; Definiciones en MK64F12.h

UART Data Register Write = Transmit

UART Data Register Read = Recieve

UART Status Register TDRE : Transmit Data Register Empty Ejemplo: void UART_Send_Data(unsigned char tx_data) { while(((UART0->S1)& UART_S1_TDRE_MASK) ==0); //Puedo Transmitir ? UART0->D = tx_data; // Transmito }

UART Status Register RDRF : Recieve Data Register Full Ejemplo: Un programa que hace eco while(1) { if (((UART0->S1)& UART_S1_RDRF_MASK)) // Si llego algo ch=UART0->D; // Lo leo y lo retransmito while(((UART0->S1)& UART_S1_TDRE_MASK) ==0); UART0->D = ch; }

UART Interrupts UART0_LON_IRQn = 30, /**< UART0 LON interrupt (ECHELON) */ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ OR

UART Interrupts UART0_LON_IRQn = 30, /**< UART0 LON interrupt (ECHELON) */ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ OR

UART Interrupts NVIC Programming NVIC_EnableIRQ(UART0_RX_TX_IRQn);

UART Interrupts Enable Receive Interrupts on UART UART0->C2=UART_C2_TE_MASK | UART_C2_RE_MASK | UART_C2_RIE_MASK; __ISR__ UART0_RX_TX_IRQHandler (void) { unsigned char tmp; tmp=UART0->S1; // Read Status rx_flag=true; // Signal new data is ready rx_data=UART0->D; // Read Received Data } No olvidar !! Para borrar el Flag RDRF 1 Read Status 2 Read Data En ese orden