CEC 220 Digital Circuit Design Dice Game Wed, April 06 CEC 220 Digital Circuit Design Slide 1 of 15

Lecture Outline Wed, April 06 CEC 220 Digital Circuit Design Dice Game  A complex Word Problem Slide 2 of5

Dice Game Wed, April 06 CEC 220 Digital Circuit Design Implement the following dice game: 1.First Roll: Two die are thrown  The player wins if the sum is 7 or 11,  The player loses if the sum is 2, 3, or 12, otherwise  The sum is stored and referred to as the “point” and he/she must throw again. o Las Vegas Rules: The point remains fixed. 2.Second or Subsequent Roll: Two die are thrown  The player wins if the sum is equal to his/her point,  The player loses if the sum is equal to 7, otherwise  He/she must roll again until a win or loss. Slide 3 of5

Dice Game Wed, April 06 CEC 220 Digital Circuit Design Top level Interpretation  Control block is a State machine Slide 4 of5

Dice Game Wed, April 06 CEC 220 Digital Circuit Design First Problem:  How to generate a “random” roll of two dice?  Assume that the Roll signal is held high for a “long” time  Many possibilities  Must preserve “randomness” 1.A modulo 36 counter 2.Two Modulo 6 counters 3.Rising and falling edge latches 4.… Roll Slide 5 of5

Dice Game Generate the Roll signal Wed, April 06 CEC 220 Digital Circuit Design Roll signal  Pushbutton Vcc Roll = BTN3 Counting (button pressed) Not Counting Not Counting Random Duration A normally-open SPST momentary switch Slide 6 of5

Dice Game Generate a “random” roll of two dice Wed, April 06 CEC 220 Digital Circuit Design S11 D1=1,D2=1 S12 D1=1,D2=2 S16 D1=1,D2= S21 D1=2,D2=1 S22 D1=2,D2=2 S26 D1=2,D2= S61 D1=6,D2=1 S62 D1=6,D2=2 S66 D1=6,D2= A 36-state FSM clocked on the rising edge and Roll = ‘1’ Slide 7 of5

Dice Game Generate a timing diagram Friday, April 03 CEC 220 Digital Circuit Design Dice Roll Timing Diagram Clock Roll D1 State ?? 0 D2 0 Slide 8 of5

Dice Game Wed, April 06 CEC 220 Digital Circuit Design Top level Interpretation  Control block is a State machine  Inputs: o D7 = 1 is sum of dice is 7 o D711 = 1 if sum of dice is 7 or 11 o D2312 = 1 if sum of dice is 2, 3, or 12 o Eq = 1 if sum of dice is eq point reg o Rb = 1 when roll button is pressed o Reset = Async reset button  Outputs: o Roll = 1 is the counter enable o Sp = 1 causes sum to be stored in store point register o Win = 1 denotes a win o Lose = 1 denotes a loss Slide 9 of5

Dice Game – State Graph Design based on textbook solution (page 672): Wed, April 06 CEC 220 Digital Circuit Design StartS Roll1 S wait Rb/0,0 S Roll2 Rb/Roll,0 S Lose Lose S Win Win /0,0 Rb/0,0 RESET A Mealy Machine Clock on Falling Edge of 50 MHz clock Clock on Falling Edge of 50 MHz clock Outputs: o Roll = 1 enables the counter o Sp RISING edge latches “point” o Win = 1 denotes a win o Lose = 1 denotes a loss Slide 10 of5

Dice Game Generate a timing diagram Friday, April 03 CEC 220 Digital Circuit Design Dice Roll Timing Diagram Clock Rb Sum State D1,D2 Roll1 … … … Slide 11 of5

Dice Game – State Graph Design based on textbook solution (page 672): Wed, April 06 CEC 220 Digital Circuit Design S Roll1 Sp S Roll2 S Lose Lose S Win Win RESET Clock on Falling Edge of delayed Roll signal Clock on Falling Edge of delayed Roll signal A Moore Machine Outputs: o Sp FALLING edge latches “point” o Win = 1 denotes a win o Lose = 1 denotes a loss Slide 12 of5

Dice Game Generate a timing diagram Friday, April 03 CEC 220 Digital Circuit Design Dice Roll Timing Diagram Clock Rb Sum State D1,D2 Roll1 … … … Slide 13 of5

Dice Game – Debouncing a Switch Wed, April 06 CEC 220 Digital Circuit Design When are the various signals stable?  On which clock edge are they changing?  Should we try to read signals when they are changing? How can we debounce a switch  What type of switch ? o SPDT, SPST, …  If a SPDT switch then we might be able to use an S-R latch o See prior notes (latches and FFs) Slide 14 of5

Next Lecture Wed, April 06 CEC 220 Digital Circuit Design State Machine Design with SM Charts Slide 15 of5