Introduction to IC Design Tsung-Chu Huang (黃宗柱) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2003/11/17

Outline CMOS Logic Structures Clocking Strategies I/O Structures Low-Power Design

CMOS Logic Structures Fully/Partially Complementary Logic BiCMOS Logic Pseudo-nMOS Logic Dynamic CMOS Logic Clocked CMOS Logic Pass-Transistor Logic Domino Logic Cascade Voltage Switch Ligic Source Follower Pull-up Logic

Complementary MOS Logic CMOS Logic Structures Complementary MOS Logic P-Network N-Network F X

CMOS Logic Structures Compared with Bipolar Logics: BiCMOS Logic Compared with Bipolar Logics: CMOS Logics: Low power (IDDQ→0) Poor drive capability Basic idea of BiCMOS Inverter: IN

CMOS Logic Structures A BiCMOS Inverter IN 1

CMOS Logic Structures NMOS Inverter VDD Depletion mode OUT Enhance VSS Depletion mode Enhance mode

CMOS Logic Structures NMOS Circuit Body Effect!

CMOS Logic Structures NMOS Circuit

CMOS Logic Structures Pseudo-nMOS Logic IN OUT VDD VSS N-Network

Pass-Transistor and Transmission Gate High-Z or Vth-Degrade PASS Transistor Logic Circuit Pull-up or Pull-down PASS Transistor Logic Circuit A B

Source Follower Pull-up Logic (SFPL) CMOS Logic Structures Source Follower Pull-up Logic (SFPL) F A B C D Fanin↗→Co↗ Discharging via Positive-Feedback at Inputs

TTL-Interface Inverter CMOS Logic Structures TTL-Interface Inverter IN OUT VDD VSS 0.8V 2.0V

General Dynamic CMOS Logic CMOS Logic Structures General Dynamic CMOS Logic General Dynamic CMOS Logic: IDD Path is turned off when clock-disabled and/or the output is evaluated when clock-enabled. In general: Basic Dynamic CMOS n-Logic. Basic Dynamic CMOS p-Logic. Clocked CMOS Logic. Domino Logic

Basic Dynamic CMOS Logic with n-Logic CMOS Logic Structures Basic Dynamic CMOS Logic with n-Logic IN OUT VDD VSS N-Logic Block CLK Precharge Evaluate

Erroneous Evaluation in Cascaded Dynamic n-Logics CMOS Logic Structures Erroneous Evaluation in Cascaded Dynamic n-Logics IN VDD N-Logic 1 CLK N-Logic 2 They are evaluated at the same clock edges. Even slow evaluation may be impossible if the output has been discharged by pre-charged inputs. Complementary Clocked, Non-inverting or Zipper

Clocked CMOS Logic (C2MOS) CMOS Logic Structures Clocked CMOS Logic (C2MOS) IN VDD VSS P-Network N-Network OUT IN VDD VSS P-Network N-Network OUT

A primitive in Verilog: notif1 CMOS Logic Structures Tri-State Inverter IN OUT VDD VSS C A primitive in Verilog: notif1

CMOS Logic Structures Domino Logic VDD N-Logic 1 CLK N-Logic 2 The output won’t be discharged by pre-charged inputs. Evaluation (clock) time should be > tr X #stages Limitations: Buffer, non-inverting, charge redistribution

CMOS Logic Structures Wave Logic The timing is much critical. delay The timing is much critical. Very low immunity.

CMOS Logic Structures Domino Logic VDD N-Logic 1 CLK IN VDD N-Logic 1 CLK A weak pull-up p-device is used to balance the threshold and to make it static. The weak device is fed back -- a latch-version .

NP Domino Logic (Zipper CMOS) CMOS Logic Structures NP Domino Logic (Zipper CMOS) IN VDD N-Logic 1 CLK P-Logic 2 Dynamic circuit, small area, small parasitic capacitance; Glitch-free if designed carefully.

Multi-output Domino Logic (MODL) CMOS Logic Structures Multi-output Domino Logic (MODL)

Charging Sharing Problem in Domino Logic CMOS Logic Structures Charging Sharing Problem in Domino Logic

Address Decoder using Pass Transistor CMOS Logic Structures Address Decoder using Pass Transistor

Cascade Voltage Switch Ligic (CVSL) CMOS Logic Structures Cascade Voltage Switch Ligic (CVSL) VDD Switch-Logic Can be minimized; Can be implemented in clocked version, wt pulled/latched devices.

Clocking Strategies Clocked System Latch and Registers System Timing (Constraint) Single-Phase Memory Phase Locked Loop Clock Techniques Metastability and Synchronization Failure Single-Phase Logic Structure Two-Phase Clocking Two-Phase Memory Structure Two-Phase Logic Structures Four-Phase Clocking Four-Phase Memory Structures Four-Phase Logic Structures Clock Distribution

Clocking Strategies Clocked System Considerations: Independent Clock Count Clock phase count for each independent clock Clock domains Synchronous or Asynchronous Clock-Generator: Jitter Distance route → Skew → PLL, H-tree, reverse .. Toggle rate, data rate, DDR Transparency problems Meta-stability Gating Latch, FF, Register Static or Dynamic What else …

Huffman Model for a Finite State Machine Clocking Strategies Huffman Model for a Finite State Machine Q D Combinational Circuit PI: Primary Inputs PPI: Pseudo PI PO: Primary Outputs PPO: Pseudo PO Clk M L N

Basic Loop Timing Constraints Clocking Strategies Basic Loop Timing Constraints T Q D setup hold C

Timing Constraints Considering Jitter & Skew Clocking Strategies Timing Constraints Considering Jitter & Skew Q D Clk Jitter Skew

Latch Function Level-Enabled (E, EN, Enable, Clk) Function: Q=D if E=1 No Change if E=0 D Q EN High-Level Enabled D Q EN Low-Level Enabled

RS Latch S R S R S R

D Latch Static: 1 D EN 1 D EN Weak-Static: D Q Dynamic:

Multiplex (review) A B C Z 1 A B C A B

Multiplex Layout A B

Flip-Flops Function Edge-Triggered Usually consisted of a low- and a high latches D Q EN D Q EN D Q D Q

A small-area static positive-edge D Flip-flop (Vdd>2Vt) Flip-Flops A small-area static positive-edge D Flip-flop (Vdd>2Vt) D Clk Q

Synchronous v.s. Asynchronous Control Settable, Resettable, etc. Q With Clk in the path to Q Control Q No Clk in the path to Q Structural always @(posedge Clk) if(Control) Controlled_state; else Clocked_circuit; always @(posedge Clk or posedge Control) if(Control) Controlled_state; else Clocked_circuit; Behavioral

Discussion on HW#2 & Midterm Exam Home work #2: Transistor Sizing Automatically Dichotomy sizing using C scripts Exhaustively alternating using .alter How to grep, analyze and justify the results using C scripts