Features of the PIC18 microcontroller - 8-bit CPU - 2 MB program memory space (internal 32KB to 128KB) bytes to 1KB of data EEPROM - Up to 4096 bytes of on-chip SRAM - 4 KB to 128KB flash program memory - Sophisticated timer functions that include: input capture, output compare, PWM, real-time interrupt, and watchdog timer - Serial communication interfaces: SPI, I2C - Background debug mode (BDM) - 10-bit A/D converter - Memory protection capability - Instruction pipelining - Operates at up to 40 MHz crystal oscillator

Features of PIC18 ̶ 5 input/output Port (PORT A,B,C,D & E) ̶ Synchronous Serial Port (SSP) with SPI (master code) and I2C (master/slave). ̶ Universal Synchronous Asynchronous Receiver Transmitter (USART) with 9 bit address detection. ̶ Parallel Slave Port (PSP) 8 bit wide with external RD, WR and CS controls (40/46pin). ̶ Brown Out circuitry for Brown-Out Reset (BOR). ̶ In-circuit serial programming and in-circuit debugging capability

Architecture of PIC18

Microprocessor Unit Includes Arithmetic Logic Unit (ALU), Registers, and Control Unit ◦ Arithmetic Logic Unit (ALU)  Instruction decoder  16-bit instructions  Status register that stores flags  5-bits  WREG – working register  8-bit accumulator

Microprocessor Unit ◦ Registers  Program Counter (PC)  21-bit register that holds the Program Memory address  Bank Select Register (BSR)  4-bit register used in direct addressing the Data Memory  File Select Registers (FSRs)  12-bit registers used as memory pointers in indirect addressing Data Memory ◦ Control unit  Provides timing and control signals  Read and Write operations 330_026

Microprocessor Unit ◦ Registers  Program Counter (PC)  21-bit register that holds the Program Memory address  Bank Select Register (BSR)  4-bit register used in direct addressing the Data Memory  File Select Registers (FSRs)  12-bit registers used as memory pointers in indirect addressing Data Memory ◦ Control unit  Provides timing and control signals  Read and Write operations 330_027

PIC18F - Address Buses Address bus ◦ 21-bit address bus for Program Memory  Addressing capacity: 2 MB ◦ 12-bit address bus for Data Memory  Addressing capacity: 4 KB Data bus ◦ 16-bit instruction/data bus for Program Memory ◦ 8-bit data bus for Data Memory Control signals ◦ Read and Write 330_028

PIC18F452/4520 Memory Program Memory: 32 K to 128K ◦ Address range: to 007FFF H Data Memory: 4 K ◦ Address range: 000 to FFF H Data EEPROM ◦ Not part of the data memory space ◦ Addressed through special function registers 330_029

MCU Support Devices Timers ◦ Capture, Compare and PWM (CCP Modules) Serial Communications ◦ Master Synchronous Serial Port (MSSP) ◦ Addressable USART A/D converter Parallel Slave Port (PSP) Data EEPROM 330_0210

Memory Organization

PIC 18 - CPU

CPU Registers

CPU registers STATUS Register

PIPELINING

PIPELINING

PIPELINING

PIPELINING

PIPELINING

PIPELINING

PIPELINING

PIC18 Instruction Format

PIC18 Addressing Modes PIC18 Addressing Modes

PIC18 Instruction Set

Interrupt

Interrupt Structure

Interrupt Operation

Core Group

Interrupt Operation without Setting Priority

Interrupt Operation with Priority Enabled

Interrupt Operation

Reset operation

Parallel Ports

Input/output ports PIC18F has 5 basic input/output ports. They are usually denoted by PORT A (RA), PORT B (RB), PORT C (RC), PORT D (RD), and PORT E (RE). These ports are used for input/ output interfacing All these ports are bi-directional. The direction of the port is controlled by using TRIS(X) registers (TRIS A used to set the direction of PORT-A, TRIS B used to set the direction for PORT-B, etc.) Parallel Ports

Each port has three registers for its operation. These registers are: TRIS register (data direction register) PORT register (reads the levels on the pins of the device) LAT register (output latch) PORTA, TRISA and LATA Registers  PORTA is an 7-bit wide, bidirectional port.  The corresponding data direction register is TRISA.  Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode).  Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output

Parallel Ports PORTB, TRISB and LATB Registers  PORTB is an 8-bit wide, bidirectional port.  The corresponding data direction register is TRISB.  Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode).  Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output

Parallel Ports PORTC, TRISC and LATC Registers  PORTB is an 7-bit wide, bidirectional port.  The corresponding data direction register is TRISC.  Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode).  Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output

Parallel Ports PORTD, TRISD and LATD Registers  PORTD is an 8-bit wide, bidirectional port.  The corresponding data direction register is TRISD.  Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode).  Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output

Parallel Ports PORTE, TRISE and LATE Registers  PORTE is an 4-bit wide, bidirectional port.  The corresponding data direction register is TRISE.  Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode).  Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output  Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPP and RE2/AN7/OESPP) are individually configurable as inputs or outputs.