Effects of Signal Return Path Discontinuity (RPD) & SSN One signal switching without reference plane change power via L G P L G P P G One signal switching.

Slides:

Advertisements

Similar presentations

1 Designing for DVI General Applications Considerations.

Advertisements

Modeling and Design for Beyond-the-Die Power Integrity

We begin by subtracting noise (run flash lamp without HV) from signal (run flash lamp with HV) In the above for the cathode, we subtract the brown noise.

1CADENCE DESIGN SYSTEMS, INC. Using Allegro PCB SI to Analyze a Board’s Power Delivery System from Power Source to Die Pad International Cadence Usergroup.

ECEN 5004 – Digital Packaging Chapter 4 “Fundamentals of Electrical Package Design” Objectives: Introduction to electrical package design Signal integrity,

® WPD WORKSTATION PRODUCTS DIVISION 1 Page 1 IEEE EPEP2000 Via and Return Path Discontinuity Impact on High Speed Digital Signal Qinglun Chen, Intel WPD.

Chapter 15: Data Transmission Business Data Communications, 5e.

Physics 262 Website: Exams: 7 midterms, scantron but not multiple choice Drop lowest.

High speed digital systems Project Status D0913 Avital Katz Elad Yaniv D0913 Avital Katz Elad Yaniv.

Lecture 24: Interconnect parasitics

MB4 New compared with MB3: Digital drivers / transformer drivers options 14 OPAMPS instead of 4 Thinner coaxial cables Shorter umbilical Heater coil integrated.

Neurons – Biological Digital Circuits

Basics in Magnetism Electromagnetism Force on a Current-Carrying Wire EM Induction Transformer Generators Electric Motors ELECTROMAGNETISM.

AZIZ112/MAPLD2004 Printed Circuit Board Simulation: A Look at Next Generation Simulation Tools and Their Correlation to Laboratory Measurements Shahana.

Differential Signals EECS 713 Project by Jay Fuller :) What are they? When to use them Traces, connectors, terminations, etc.

Layout Considerations of Non-Isolated Switching Mode Power Supply

Taking the Mystery out of Signal Integrity

Chapter 15: Data Transmission Business Data Communications, 6e.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 38: December 3, 2014 Transmission Lines.

Unit 3 Waves and Light Lesson 3: The Electromagnetic Spectrum

PCB Layout Introduction

EECS 498 Advanced Embedded Systems Lecture 8: Topic Groups, RTOS Review & Power Introduction.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: December 5, 2012 Transmission Lines.

PCB Layout Introduction

Power Distribution Networks

Ring Oscillator in Switched Capacitor Feedback

Mechanical Modeling The dynamic response is give by d’Alembert principle and is From this equation the switching time, mechanical bandwidth and and effect.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: November 24, 2014 Inductive Noise.

Optical Gigabit Ethernet Group F.O.R.E. Final Presentation Chris Abbott, Ronen Adato, David Larado 4/21/2005.

Physical Layer Continued. Review Discussed how to design the communication scheme depending on the physical mediums – pulling voltage up and down for.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 32: November 28, 2011 Inductive Noise.

Impact of High Impedance Mid-Frequency Noise on Power Delivery Jennifer Hsiao-Ping Tsai.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: November 25, 2013 Inductive Noise.

E-Cal Readout Boards - 8 Boards total -Design & Fabrication at Jlab - Assembly at Orsay Nick Nganga HPS Collaboration Oct Jlab.

Global Circuit Page 1  Basic Design Rule for Advanced PCB (1) 1. High speed current path Load Driving gate Current trace At low frequency current, follows.

EECS 713 Project Instructor: Prof. Allen Presented by: Chen Jia.

Exam 1 information Open book, open notes, bring a calculator Eligible topics (1 of 2) (not an exhaustive list) Everything covered up to and including transmission.

Seraj Dosenbach Greg Lammers Beau Morrison Ananya Panja Printed Circuit Board Layout Narrative plus Preliminary PCB Layout.

Power Line Communication for Hybrid Power/Signal Pin SOC Design CK Cheng CSE Dept, UC San Diego.

Exam 2 information Open book, open notes, bring a calculator Wednesday Dec 16, 10:30 to 1:00 pm Eligible topics (1 of 3) (not an exhaustive list) Exam.

1 1. Provide better power/ground distribution Increased static capacitance due to thinner core Lower power/ground plane transient impedance due to larger.

Chapter 2. High-speed properties of logic gates.

Maxwell’s Equations. Four equations, known as Maxwell’s equations, are regarded as the basis of all electrical and magnetic phenomena. These equations.

Waveform 1.1 Basic Digital Waveform Parameters 1 Paul Godin Updated December 2014.

THEMIS Instrument CDR 1 UCB, April 20, 2004 Actel Reliability Critical Design Review Robert Abiad University of California - Berkeley.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 31: November 22, 2010 Inductive Noise.

MICROPROCESSOR DESIGN1 IR/Inductive Drop Introduction One component of every chip is the network of wires used to distribute power from the input power.

Piero Belforte, HDT High Design Technology presentation by Alessandro Arnulfo (1998).

Piero Belforte, HDT 1999: PRESTO POWER by Alessandro Arnulfo.

High Speed Properties of Digital Gates, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology

HDT, 1998: Resistance, Inductance, Capacitance, Conductance per Unit Length Lossless case.

Piero Belforte, HDT, July 2000: MERITA Methodology to Evaluate Radiation in Information Technology Application, methodologies and software solutions by Carla Giachino,

Piero Belforte 2012: HiSAFE+ MULTIGIGABIT FAULT INSERTION TESTER

GaAs Process & Devices Anurag Nigam.

Day 38: December 4, 2013 Transmission Lines Implications

Copyright © American Speech-Language-Hearing Association

Preliminary PCB Design

High-Speed Serial Link Layout Recommendations –

How to debug PMP systems A guideline for Application Engineers

Harmonics Ben Kemink.

Electromagnetic Compatibility BHUKYA RAMESH NAIK 1.

Open book, open notes, bring a calculator

Basic Check-out of a Controller Area Network (CAN) Bus

Open book, open notes, bring a calculator

High-Speed Serial Link Layout Recommendations –

First slides: Prof. Stojanovic, MIT Last slides: Prof. Dally, Stanford

Tri-state Buffers and Drivers By Taweesak Reungpeerakul

Durel IC Drivers All Durel drivers are available as bare die, or in MSOP8 package form in tape and reel. The Durel D340 is the smallest IC available.

XMBTM Product 10 Gbps Backplane using Multiwire ® Technology

Some electrical issues related to the building of PCBs

Presentation transcript:

Effects of Signal Return Path Discontinuity (RPD) & SSN One signal switching without reference plane change power via L G P L G P P G One signal switching with reference plane change, Red:signal current Blue:Displacement return current Pink:power/ground voltage fluctuation in the form of EM wave Multiple signals switching with reference plane change, Red: more signal currents Pink: stronger power/ground voltage fluctuations in the form of EM wave, more signal waveform distortion and skew

Receiver Waveform under the Influence of Simultaneous Switching Noise (SSN) (As the Number of Simultaneous Switched Drivers Varies, no decoupling caps used, results from Speed2000) Ideal Case: Trace in top layer, no RPD 8 Drivers 4 Drivers 1 Driver skew ringing Timing and waveform degradation are THE 2 things in SI study. Pwr/gnd as signal RPD affect both through basic EM phenomena.

Effect of Decoupling Caps on Receiver Voltage with 8 Drivers Switching Simultaneously (SSN reduction, results from Speed2000) Ideal case: Trace on Top layer, no RPD 32 caps (0603) plus 4 caps (0805) No decoupling caps 4 caps (0805) Max Overshoot/Undershoot No decoupling caps: 772 mV 4 caps: 260 mV 36 caps: 49 mV Ideal case: 39 mV

The Electromagnetic Interactions Take Place Inside Packaging Structures