Advanced Computing and Information Systems laboratory Nanocomputing technologies José A. B. Fortes Dpt. of Electrical and Computer Eng. and Dpt. of Computer and Information Sci. and Eng. University of Florida, Gainesville

Advanced Computing and Information Systems laboratory Nanocomputing Computing with nanoscale devices 1 nm = µm = width of 10 H atoms = diameter of sugar molecule devices/cm – 1000 billion-device chips 1 – 50 nanometer device features CMOS faces difficult challenges above 65 nm and extremely hard/expensive ones below 65 nm (Source:ITRS) Year DRAM½ Pitch Ggate, Gbit, GHz bottom-up built FPGA/RAM nanoarrays by

Advanced Computing and Information Systems laboratory Nanotechnology: A Convergence of Enabling Technologies Dimension (nm) 0.1nm 1 nm 10 nm 100 nm 1  m 100  m 10  m Simple Molecules Atoms Gate Length in CMOS Device Dimension in CMOS Biological Cell Microelectronics Oxide Thickness in CMOS Downscaling Chemical/Biological Synthesis Nanoclusters Building Imaging/Manipulation of Structures Scanning Probes Electron Microscopy Optical Microscopy Voltage Control *This slide provided by D. Janes

Advanced Computing and Information Systems laboratory Towards nanoscale CMOS Transistor gate scaling silicide Strained Si Intel: Aug 02, Spectrum Oct 02, 02 International Electron Devices Meeting (IEDM), Dec nm SiO

Advanced Computing and Information Systems laboratory Barriers to “CMOS as usual” Source: G. Bourianoff

Advanced Computing and Information Systems laboratory Many challenges MOS PERFORMANCE AND LEAKAGE [PROCESS INTEGRATION, DEVICES, AND STRUCTURES] PRODUCTION OF NON-CLASSICAL CMOS [FRONT END PROCESSES] POWER MANAGEMENT [DESIGN] HIGH-SPEED DEVICE INTERFACES [TEST AND TEST EQUIPMENT] COORDINATED DESIGN TOOLS AND SIMULATORS TO ADDRESS CHIP, PACKAGE, AND SUBSTRATE CODESIGN [ASSEMBLY AND PACKAGING] … Source: ITRS 2001

Advanced Computing and Information Systems laboratory Meindl’s perspective (1) Hierarchy of physical limits fundamental, material, device, circuit, system System: Architecture, switching energy, heat removal, clock frequency and chip size potential for TSI > 1 trillion transistors/chip 2-gate transistor, 10-nm/3-nm channel length/thickness, 1-nm gate oxide Science, vol. 293, Sep 2001

Advanced Computing and Information Systems laboratory Meindl’s perspective (2) Wire vs. transistor in state-of-the-art 100-nm technology 6 times the latency, 5 times the energy Tyranny of interconnects Equal latency for superconductive 30-  m interconnect with vacuum insulator and 10-nm transistor Larger switching energy Moore’s law to continue via interconnect improvements Better-than-silicon technologies must be interconnect centric

Advanced Computing and Information Systems laboratory System design challenges Vanishing design spaces for existing paradigms and revolutionary technologies that may not be well suited for conventional logic and architectures Interconnect-limited performance Local connections desirable – but not enough A function of how system uses interconnect

Advanced Computing and Information Systems laboratory Emerging technologies Nanocomputing taxonomy Source: The future of nanocomputing, G. Bourianoff, Computer, 8/03

Advanced Computing and Information Systems laboratory Chiseling: Start with a relatively uniform, large piece of material --selectively shape/remove material to define desired object. Building: Start with small building blocks; combine and arrange them to form interesting assemblies Builders versus Chiselers: a Historical View *This slide provided by D. Janes

Advanced Computing and Information Systems laboratory Chiseling: Use lithography, etching, etc. to define devices, interconnects Yields well optimized device structures, nearly arbitrary interconnect configurations Building: Use chemical affinities, etc. to form controlled assemblies of atoms, molecules, clusters Potentially fast, flexible, able to generate nanometer scale structures Builders versus Chiselers -- Micron to Atomic Scale Au Ag Nanoclusters + Molecules XX Y Structure Au Ag Self-Assembly Si Substrate PMOS deviceNMOS device Lithography, etching, implant *This slide provided by D. Janes