SBS/A1n Fast DAQ Alexandre Camsonne October 19 th 2012

Outline Overview Experiments Channel count Fastbus inventory Test stand Module flipping CODA 3 / Intel CPU MPD APV25 Questions To do / timeline Conclusions

Overview Mixed DAQ using VME for GEM readout and Fastbus for other detectors Use multiple crates and modules to reduce deadtime

Fastbus A1n : Big Bite – Lead Glass – 4 Fastbus crates GEn / GMn – BigBite 4 Fastbus crates – Cdet : 8 Fastbus crates Gep : – BigCal : 6 Fastbus crates – Cdet : 8 Fastbus crates

Experimental rates A1nGepGenGMnSIDIS Singles BB10 KHzX2KHz1KHz200 KHz Singles e-200KHz??5 KHz Singles hadron X1.5 MHz1.3 MHz1MHz3 MHz CoincX3 KHz65 Hz50 Hz~1KHz Trigger rate 10 KHz3 KHz2 KHz1KHz

Channel count A1nGepGenGMnSIDIS BigBite243 LG 550 Cer 90x2 Scint = LG 550 Cer 90x2 Scint = LG 550 Cer 90x2 Scint = LG 550 Cer 90x2 Scint = 873 HCALX242 CDet3328 X ECALX1520 Shower XXx RICHXXXX1934 Total GEM

Channel count A1nGepGenGMnSIDIS BigBite243 LG 550 Cer 90x2 Scint = LG 550 Cer 90x2 Scint = LG 550 Cer 90x2 Scint = LG 550 Cer 90x2 Scint = 873 HCALX242 CDet3328 X ECALX1520 Shower XXx RICHXXXX1934 Total GEM

Bigbite spectrometer 10/13/2011 SuperBigbite DAQ and Electronics Alexandre Camsonne 9 Bigbite Standard Hall A equipment spectrometer used for to E GE n, Same setup for 12 GeV A 1 n experiment and 12 GeV GE n and GM n Shower counter 7x27 blocks Preshower 2x27 blocks 243 blocks total Analog sum on shower and preshower all modules available and used in previous experiments

SuperBigbite Spectrometer Focal Plane Polarimeter setup 10/13/ SuperBigbite DAQ and Electronics Alexandre Camsonne

Fastbus SFI – Hall A : ( TEDF ) + 1 (EEL ) – Hall B : 5 (+ 11 available if DC upgrade ) – DAQ group : 1 – 6 CLEO FRITZ SFI but no driver / software Crate / Power supply – 3 BigBite – 2 TEDF – 5 + (11 ) Hall B – 2 RCS ? – 1 EEL – 2 HRS New – power supplies : 10 K$ – SFI : 9 K$ – Intel VME CPU : 3.5 K$ Need to check for Geographical and Arbitration controller board 11 SFI + 4 spares 10 powers supplies + 3 spares Need 6 power supplies and 18 Fastbus blowers

Test stand 2 Fastbus Crate and PS from Hall B OSP done CODA running from 2 SFI with Intel VME CPU TS and VME64X crate to be installed Error on boards – Interference of TI with Fastbus, one bug fixed with new TI ( missing interrupt line ) – Possibly some other issues between SFI and VME TI – Debugging

Module flipping Send signals to several modules to reduce encoding deadtime Use ribbon cable with daisy chaining Signal

Module flipping V1495 programming – Use Compton prescaler as starting point L1A Prescale N L1A on output Ntrig modulo N Fast Clear Busy out Front End Busy Fast Clear on output Ntrig modulo N Fastbus modules x N

Module flipping V1495 programming – First version working should be good enough to evaluate dead time improvement – Need implement busy logic and fast clear – Want to implement FIFO to store state for readout and TDC output with board status for sync check – Need to check synch and timing resolution

Intel CPU Installed Linux operating system on Compact Flash so board can boot stand alone Readout of Fastbus working Trigger with old VME TI with SFI working trying new TI to test improvement with event blocking Develop code for Fastbus readout with new TI Develop code for module flipping readout Port MPD code to Intel CPU

MPD / APV25 MPD working with APV25 using CAEN controller MPD boards in UVA for GEM testing Move APV setup to JLAB after test Adapt Evaristo’s library for use with CODA using Intel VME CPU

MQT 16 channels per board Current drawn to be determined Additional cost of MQT power supplies most likely similar to Fastbus PS with FAN about 11 K$ Detector

To do / timeline Evaluate performance of module flipping using old VME CPU and EEL setup ( 1 week ) Evaluate performance with Intel CPU ( 2 weeks ) in TEDF Setup Trigger supervisor add Fastbus bin : test setup with multiple crates ( 1 week ) Check data integrity and implement sync check ( 2 weeks )

To do / timeline Port MPD library to use with CODA ( 3 weeks ) Test full A1n setup Add additional crates for SBS running Develop HCAL trigger Test coincidence trigger ………………………

Tasks Test GAC, ATC board Test SFI V1495 Module flipping programming Test Intel CPU

Research Man Power GEM readout APV25 / VME – INFN : Evaristo Cisbani, 1 technician – NSU : Mahbub Kandaker, Vina Punjabi Front End NINO chips – Glasgow : John Annand Hadron calorimeter trigger and trigger logic – Ron Gilman, 1 postdoc, 1 student – Jefferson Laboratory : Ole Hansen, Alexandre Camsonne Electron calorimeter trigger – Jefferson Laboratory : Mark Jones, Alexandre Camsonne – William and Mary : Charles Perdrisat Hall A infrastructure – DAQ computer : Ole Hansen – Network : JLAB network 10/13/2011 SuperBigbite DAQ and Electronics Alexandre Camsonne 22

Time line 2012 – GEM + APV25 GEM tests during g2p – FADC tests – Receive BELLE Fastbus electronics + MQT – 4 JLAB FADC – Small scale setup for testing : FADC + trigger + Fastbus + APV25 – All APV25 and MPD for GE n built and tested by NSU 2014 – MPD GEM electronics installed on detectors for A1n – Start Gep electronics – Start Hadron Calorimeter Trigger implementation Digital Trigger electronics test parasitic 2015 – Run A1n 2016 – Hadron Calorimeter complete – Full DAQ setup 2017 – Ready for GE n 10/13/2011 SuperBigbite DAQ and Electronics Alexandre Camsonne 23

Conclusion Test stand in TEDF ready Basic readout of Fastbus done with Intel CPU Development of use of CODA 3 VME TI Module flipping hardware ready : need to write software and study performance. First glance at performance when buffering with TI or TS Need to develop module flipping with busy and Fast Clear Major work to make sure of data synchronization Start work on MQT Need complete Fastbus inventory ( potential shortage of GAC and ATC ) Full test of all electronics and spares Getting Hall B Drift Chamber Fastbus