VADA Lab.SungKyunKwan Univ. 1 L20 :Lower Power Booth Multiplier Design 성균관대학교 전기전자컴퓨터공학부.

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VADA Lab.SungKyunKwan Univ. 1 L20 :Lower Power Booth Multiplier Design 성균관대학교 전기전자컴퓨터공학부

VADA Lab.SungKyunKwan Univ. 2 Reduandant Binary-based Booth Multipler 곱셈은 덧셈과 함께 correlation, convolution, filtering, DFT(Discrete Fourier Transform) 등과 같은 디지털 신호 처리에 있어서 가장 많이 사용되는 연산이다. 현재 가장 많이 사용되는 곱셈기는 부분합들을 만들어 내는 인코 더부분은 Booth 인코더를, 부분합들을 더하는 adder array 에는 Wallace Tree 를 이용하는 곱셈기이다. 본 논문에서는 2 의 보수가 아닌 Redundant Binary 표현 ( -1, 0, 1 ) 을 사용하는 Booth 인코더를 제안하였고, 이를 Carry- Propagation-Free Adder 를 사용하여 부분곱들을 더하는 새로운 곱셈기를 제안하였다.

VADA Lab.SungKyunKwan Univ. 3 목 차 연구의 중요성 연구배경 Modified Booth 곱셈기 Wallace Tree - 4:2 Compressor 제안된 Carry-Propogation-Free Adder 제안된 Basic Encoding Method (BEM) 제안된 Extended Encoding Method (EEM) 제안된 곱셈의 Block Diagram 실험결과 결론 및 향후계획

VADA Lab.SungKyunKwan Univ. 4 Modified Booth 곱셈기 n Multibit Recoding 을 사용하여 부분합의 갯수를 n/2 개로 줄여 고속의 곱셈을 가능하게 한다. n 피승수 (multiplicand) : X, 승수 (multiplier) : Y Recoded digit = Y 2i-1 + Y 2i -2Y 2i+1 ( Y -1 =0 )

VADA Lab.SungKyunKwan Univ. 5 Modified Booth 곱셈기 - 예

VADA Lab.SungKyunKwan Univ. 6 Wallace Tree - 4:2 Compressor

VADA Lab.SungKyunKwan Univ. 7 Multipliers - Area 16-bit Multiplier Area

VADA Lab.SungKyunKwan Univ. 8 Multiplier - Delay Average Power Dissipation (16-bit)

VADA Lab.SungKyunKwan Univ. 9 Multiplier - Power Worst-Case Delay (16-bit)

VADA Lab.SungKyunKwan Univ. 10 Carry-Propagation-Free Adder Carry-Propagation-Free adder 는 carry propagation 의 발생없이 2 진 트리형태로 덧셈이 가능하기 때문에 고속 및 저전력을 실현할 수 있다. Carry-Propagation-Free adder 는 다음과 같은 2 단계로 구성된다 – 첫번째 단계 : intermediate sum 과 intermediate carry 를 만드는 단계 – 두번째 단계 : final sum 을 만드는 단계 첫번째 단계에서의 계산 법칙

VADA Lab.SungKyunKwan Univ. 11 제안된 Carry-Propagation-Free Adder Redundant binary 표현은 { 1, 0, -1 } 으로 구성된다. 다음과 같이 하나의 digit 를 두 개의 bits 로 표현한다. 곱셈 연산은 shift-and-add 알고리즘을 사용하기 때문에 덧셈기는 다음과 같이 세 부분으로 구성된다.

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VADA Lab.SungKyunKwan Univ. Modified Booth 곱셈기 Multibit Recoding 을 사용하여 부분합의 갯수를 1/2 로 줄여 고속의 곱셈을 가능하게 한다. 피승수 (multiplicand) : X, 승수 (multiplier) : Y Recoded digit = Y 2i-1 + Y 2i -2Y 2i+1 ( Y -1 =0 )

VADA Lab.SungKyunKwan Univ. 26 Modified Booth 곱셈기 - 예 Example

VADA Lab.SungKyunKwan Univ. 27 Wallace Tree - 4:2 Compressor

VADA Lab.SungKyunKwan Univ. 28 Multipliers - Area 16-bit Multiplier Area

VADA Lab.SungKyunKwan Univ. 29 Multiplier - Delay Average Power Dissipation (16-bit)

VADA Lab.SungKyunKwan Univ. 30 Multiplier - Power Worst-Case Delay (16-bit)

VADA Lab.SungKyunKwan Univ. Instruction Level Power Analysis Estimate power dissipation of instruction sequences and power dissipation of a program E b : base cost of individual instructions E s : circuit state change effects E M : the overall energy cost of a program B i : the base cost of type i instruction N i : the number of type i instruction O i,j : the cost occurred when a type i instruction is followed by a type j instruction N i,j : the number of occurrences when a type i instruction is immediately followed by a type j instruction

VADA Lab.SungKyunKwan Univ. Instruction ordering Develop a technique of operand swapping Recoding weight : necessary operation cost of operands W total : total recoding weight of input operand W i : weight of individual recoded digit i in Booth Multiplier W b : base weight of an instruction W inter : inter-operation weight of instructions Therefore, if an operand has lower W total, put it in the second input(multiplier).

VADA Lab.SungKyunKwan Univ. RESULT

VADA Lab.SungKyunKwan Univ. Conclusion Power[pJ] bits % of instances with circuit states effects 4.0% reduction 12.0% reduction 9.0% reduction

VADA Lab.SungKyunKwan Univ. 35 References [1] Gary K. Yeap, "Practical Low Power Digital VLSI Design", Kluwer Academic Publishers. [2] Jan M. Rabaey, Massoud Pedram, "Low Power Design Methodologies", Kluwer Academic Publishers. [3] Abdellatif Bellaouar, Mohamed I. Elmasry, "Low-Power Digital VLSI Design Circuits And Systems", Kluwer Academic Publishers. [4] Anantha P. Chandrakasan, Robert W. Brodersen, "Low Power Digital CMOS Design", Kluwer Academic Publishers. [5] Dr. Ralph Cavin, Dr. Wentai Liu, "1996 Emerging Technologies : Designing Low Power Digital Systems" [6] Muhammad S. Elrabaa, Issam S. Abu-Khater, Mohamed I. Elmasry, "Advanced Low-Power Digital Circuit Techniques", Kluwer Academic Publishers.

VADA Lab.SungKyunKwan Univ. 36 References [BFKea94] R. Bechade, R. Flaker, B. Kaumann, and et. al. A 32b 66 mhz 1.8W Microprocessor". In IEEE Int. Solid-State Circuit Conference, pages , [BM95] Bohr and T. Mark. Interconnect Scaling - The real limiter to high performance ULSI". In proceedings of 1995 IEEE international electron devices meeting, pages , [BSM94] L. Benini, P. Siegel, and G. De Micheli. Saving Power by Synthesizing Gated Clocks for Sequential Circuits". IEEE Design and Test of Computers, 11(4):32-41, [GH95] S. Ganguly and S. Hojat. Clock Distribution Design and Verification for PowerPC Microprocessor". In International Conference on Computer-Aided Design, page Issues in Clock Designs, [MGR96] R. Mehra, L. M. Guerra, and J. Rabaey. Low Power Architecture Synthesis and the Impact of Exploiting Locality". In Journal of VLSI Signal Processing,, 1996.