Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics; –delay; –power. n Effects of parasitics on gate. n Driving large loads.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Logic levels n Solid logic 0/1 defined by V SS /V DD. n Inner bounds of logic values V L /V H are not directly determined by circuit properties, as in some other logic families. logic 1 logic 0 unknown V DD V SS VHVH VLVL

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Logic level matching n Levels at output of one gate must be sufficient to drive next gate. > <

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Transfer characteristics n Transfer curve shows static input/output relationship—hold input voltage, measure output voltage.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Inverter transfer curve |slope| >1 |slope| <1 logic 1 logic 0 unknown V IH V IL V DD V SS

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Logic thresholds n Choose threshold voltages at points where slope of transfer curve = -1. n Inverter has a high gain between V IL and V IH points, low gain at outer regions of transfer curve. n Note that logic 0 and 1 regions are not equal sized—in this case, high pullup resistance leads to smaller logic 1 range.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Noise margin n Noise margin = voltage difference between output of one gate and input of next. Noise must exceed noise margin to make second gate produce wrong output. In static gates, t=  voltages are V DD and V SS, so noise margins are V DD -V IH and V IL - V SS. Noise < V DD -V IH, V IL -V SS for correct operation

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Delay n Assume ideal input (step), RC load. wire + transistor Charge when pull-up is on, discharge when pull-down is on.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Delay assumptions n Assume that only one transistor is on at a time. This gives two cases: –rise time, pullup on; –fall time, pullup off. n Assume resistor model for transistor. Ignores saturation region and mischaracterizes linear region, but results are acceptable. (In both pull-up and pull-down cases.)

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Current through transistor n Transistor starts in saturation region, then moves to linear region. (In both pull-up and pull-down cases.)

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Resistive model for transistor n Average V/I at two voltages: –maximum output voltage –middle of linear region n Voltage is V ds, current is given I d at that drain voltage. Step input means that V gs = V DD always.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Resistive approximation R n = (R s + R l )/2 RlRl RsRs

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Ways of measuring gate delay n Delay: time required for gate’s output to reach 50% of final value. n Transition time: time required for gate’s output to reach 10% (logic 0) or 90% (logic 1) of final value. (fall or rise time).

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Inverter delay circuit n Load is resistor + capacitor, driver is resistor. (Pull-down transistor is “on” case): transistor

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Inverter delay with  model  model: gate delay based on RC time constant . ( Discharging case) n V out (t) = V DD exp{-t/(R n +R L )C L }= 0.5V DD n t d = 0.69(R n +R L )C L n t f = - (R n +R L )C L ln 0.1/0.9 = 2.2 (R n +R L )C L n (Use 0.1 V DD and 0.9 V DD ) n For pullup time, use pullup resistance.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR  model inverter delay n 0.5 micron process: –R n = 3.9 k  –C L = 0.68 fF n So –t d = 0.69 x 3.9 x.68E-15 = 1.8 ps. (delay) –t f = 2.2 x 3.9 x.68E-15 = 5.8 ps. (fall time)

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Quality of RC approximation

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Quality of step input approximation

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Results of using small pullup

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Other models n Current source model (used in power/delay studies): –t f = C L (V DD -V SS )/I d (relies on capacitive charging or discharging without a resistor assuming a current source model of a transistor.) – = C L (V DD -V SS )/0.5 k’ (W/L) (V DD -V SS -V t ) 2 n Fitted model: fit curve to measured circuit characteristics.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Body effect and gates n Difference between source and substrate voltages causes body effect. n Source for gates in middle of network may not equal substrate: (This causes an upward shift in the threshold (turn on) voltage of the transistor. Consequently, transistors closer to the power supply have a higher threshold to turn on. Therefore connecting those signals that arrive early to transistors closer to the power supply will give them more time to turn their transistors on or off and match the arrival times of late arriving signals. ) 0 0 Source above VSS Body effect capacitance

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Body effect and gate input ordering n To minimize body effect, put early arriving signals at transistors closest to power supply: Early arriving signal

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Power consumption analysis n Almost all power consumption comes from switching behavior. n Static power dissipation comes from leakage currents. n Surprising result: power consumption is independent of the sizes of the pullups and pulldowns. (Please see pp in textbook.)

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Power consumption circuit n Input is square wave.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Power consumption n A single cycle requires one charge and one discharge of capacitor: E = C L (V DD - V SS ) 2. n Clock frequency f = 1/t. n Energy E = C L (V DD - V SS ) 2. n Power = E x f = f C L (V DD - V SS ) 2. n (Energy per unit time)

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Observations on power consumption n Resistance of pullup/pulldown drops out of energy calculation. n Power consumption depends on operating frequency. –Slower-running circuits use less power (but not less energy to perform the same computation). (They take longer to charge but store or remove the same amount of energy into (from) the load capacitor.)

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Speed-power product n Also known as power-delay product. n Helps measure quality of a logic family. n For static CMOS: –SP = P/f = CV 2. n Static CMOS speed-power product is independent of operating frequency. –Voltage scaling depends on this fact. (Power reduces quadratically with voltage whereas delay reduces linearly with it.)

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Parasitics and performance b a c

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Effect of parasitics n a: Capacitance on power supply is not bad, can be good in absence of inductance. Resistance slows down static gates, may cause pseudo- nMOS circuits to fail. ( Adding a capacitance between the power supply and the pull-up transistor will reduce the total capacitive load on the next stage when charging it, and will thus decrease its charge time. Adding a resistance will increase the resistive load requiring longer time to charge since more current will dissipate through the increased resistance ) + C1C1 C2C2 C eff = C 1 C 2 / (C 1 + C 2 ) < C 1, C 2

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Effects of parasitics, cont’d n b: Increasing capacitance/resistance reduces input slope. n c: Similar to parasitics at b, but resistance near source is more damaging, since it must charge more capacitance. (It will take longer for C L to charge because, C x must be charged first.)

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Driving large loads n Sometimes, large loads must be driven: –off-chip; –long wires on-chip. n Sizing up the driver transistors only pushes back the problem—driver now presents larger capacitance to earlier stage.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Cascaded driver circuit

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Optimal sizing n Use a chain of inverters, each stage has transistors a larger than previous stage. n Minimize total delay through driver chain: –t tot = n(C big /C g ) 1/n t min. n Optimal number of stages: –n opt = ln(C big /C g ). Driver sizes are exponentially tapered with size ratio . (The total time is minimized when  = e. Thus, 2 to 3 stages give the minimum total delay when cascading two or more gates.)