LHCb Calorimeter Meeting – 2 nd December 2015 Calorimeter upgrade update Universitat de Barcelona, Institut de Ciències del Cosmos ICC-UB Laboratoirede L’accélerateurLinéaire(LAL), Orsay, France

2 Introduction Calo meetingDecember 2 nd 2015 Recently the upgrade group performed a new test beam to check the performances of the analog electronics Noise study performed in the cavern Several meetings concerning Readout Fibre Tuesday meeting session on the extension of the ET range of the ECAL See agenda at Future meeting to come Next Monday 7 dec. Improvements of th calorimeter design during the LS3

3 Test beam: linearity Calo meetingDecember 2 nd 2015 First check on linearity: Mean max value on the ICECAL output Mean value of the LeCroy Scatter plot and analysis pending 20 GeV 80 GeV 100 GeV 120 GeV Non-linearity:

4 Test beam: spill-over Calo meetingDecember 2 nd 2015 Spill-over: Signal in preceeding (T-1) and following clock cycles (T1, T2, T3, …) Should be below 1% Same ASIC PZ configuration stability? Vary E and PMT+base. Spill over at different energies:Spill over with different PMT+base:

5 Noise at the detector Calo meetingDecember 2 nd 2015 Measured noise at the detector: Nominal conditions of gain Minimum gain (1/2 of nominal gain) Only dynamic pedestal subtracted values shown Effects of Cockcroft-Walton HV sources and cables increase noise To be understood: Noise increase when detector connected not seen in current electronics Nominal gain noise (MeV) ~½ gain noise (MeV) Not connected 3,8 (1,6 LSB)4,5 (1,1 LSB) ECAL typical 6,3 (2,6 LSB)7,0 (1,7 LSB) ECAL worst case 6,9 (2,9 LSB)7,4 (1,8 LSB) HCAL typical 5,2 (2,2 LSB)6,0 (1,5 LSB) HCAL worst case 6,9 (2,9 LSB)7,5 (1,9 LSB) Calibrations Nominal gain: 2,38 MeV/LSB ~1/2 gain: 4,06 MeV/LSB

6 Readout Calo meetingDecember 2 nd 2015 Problem discovered in the processing of the TELL40 True bandwidth claimed to be 100Gbits/s In fact, it is more 2x50 Gbits/s... Several solutions envisaged Increase the number of TELL40 → very expensive 2 Proposals from Guillaume / Sébastien Increase the FPGA needed resources Not sure that they would work Cannot be tested yet Reduce the bandwidth by removing most of the empty-empty events Several points still need clarification Solution 3 would be the easiest solution Is there any reason why it should not be implemented ? A summary of the meeting will shortly be posted on the agenda

7 Fibres Calo meetingDecember 2 nd 2015 A first meeting took place last week at CERN Discussion on the type of fibres to be used for the calorimeter A proposal of architecture should be presented at a new meeting Monday 14 dec. at 2pm

8 Tuesday meeting: E T range extension proposal Calo meetingDecember 2 nd 2015 Having a similar precision at low energies (Et~100MeV, e.g. Bremstrahlung) AND at 60 GeV (Et) would most probably require a major redesign of our electronics Need probably a double gain system with 2 parallel channels (2xADC) The consequences would be Large delay (complete redesign) → difficult to imagine for 2019 Increase of the needed manpower (which is small at present) Increase of the cost Outcome of discussions in the calorimeter group From measurements → estimation of the effect of a gain reduction for physics (contact people). A major modification looks difficult to justify for processes or measurements which can be/have been done by other experiments better or for which the justification comes from a very specific corner of the phase space. The upgrade conditions could be such that the low energy physics is difficult to do anyway and the noise contribution would not be the main penalty

9 Tuesday meeting: E T range extension proposal Calo meetingDecember 2 nd 2015 Proposal 1.Feel confident that we can do low energy physics and the resolution is degraded at low gain Keep the present configuration 2.Pile-up contribution is such that other effects are negligible at low energies or the noise at low gain is better than expected 20 GeV Et range can be obtained just by re-configuring the boards (+threshold tuning) Another factor could be obtained with HV reduction for the middle and outer parts The inner part may require the usage of filters (to be checked soon). This could be done during a long shut-down. The filters could also be installed BEFORE run 3 start-up if the pile-up in this region is expected to be too large from the beginning. Notice that 1. (+/-inner filter) could be used up to and 2. beyond.

10 Front-End board design Calo meetingDecember 2 nd 2015 Design is almost done The implementation of the 8-channel blocks is achieved From the connector, the ICECAL, the ADC, the FPGA to the GBTX Optical emitters, master FPGA, GBT-SCA, clock distribution, serializer (LLT) parts to be achieved soon. Still some pending issues: Et range extensions and usage of a 14 bits ADC We would like to test that the power supplies can be easily adapted to our needs for the upgrade Plan is to use a spare PS (remember, you agreed Pascal...) V. Bobillier contacted for the test 2 prototypes foreseen. A test beam is booked for April/May. Hope to be ready on time.

11 Back up Calo meetingDecember 2 nd 2015

12 Analog channel Calo meeting Switched Integrator I TH Track- and-Hold TH Filter Current amplifier Multiplexer ADC driver PZ ʃ ʃ Drv Offset Adjustable parameters: Zin Pole Zero Gain (Cint) Offset December 2 nd 2015

13 Linearity and energy range Linearity studies with minimum gain An increase offset for the differential pair output increases the linearity range Maximum E T ~ 18 GeV Calo meeting Minimum gain, Ioff=50. Saturates for lower Et → review gain and linearity at the PZ stage in case of new ASIC version December 2 nd 2015

14 Noise and energy range Measured noise Vs. E T max: –Minimum gain (Cint = 31) –Varying offset values for extended range Calo meetingDecember 2 nd 2015