Senior Design 1 Project RNG: Radiation-Based Random Number Generator Team Oregon Chub –Ashley Donahoo –Colton Hamm –Alex Brotherston –Matt Johnson University.

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Presentation transcript:

Senior Design 1 Project RNG: Radiation-Based Random Number Generator Team Oregon Chub –Ashley Donahoo –Colton Hamm –Alex Brotherston –Matt Johnson University of Portland School of Engineering Advisor: Dr. VanDeGrift, Dr. Hoffbeck, Dr. Osterberg Industry Representative: Mr. John Haner Bonneville Power Administration

Senior Design 2 Introduction Our project generates random numbers from radioactivity Building a radiation sensor, designing a MOSIS chip and using 7-segment displays University of Portland School of Engineering

Senior Design 3 Scorecard Received all ordered parts for analog circuitry. Successfully used.abl file to burn-in the CPLD macromodel. University of Portland School of Engineering

Senior Design 4 Additional Accomplishments Completed LabVIEW tutorial Received BCD-to-7-segment decoders and 7-segment displays from Craig Henry. University of Portland School of Engineering

Senior Design 5 Plans Completely test and verify CPLD functionality. Completely test and verify 7-segment display and decoder functionality. Meet with Allen about case design. University of Portland School of Engineering

Senior Design 6 University of Portland School of Engineering Milestones StatusDescriptionOriginal Target Previous Target Present Target CompletedSubmit final.edf file19 Nov Nov 10 CompletedDesign Document v Nov 10 CompletedSimulate pulse generator, transformer, voltage multiplier, and load interfacing in PSPICE 30 Nov 10 CompletedDesign Document 1.03 Dec Nov 10 CompletedUse.abl file to create CPLD macro model 10 Dec 10 CompletedAnalog parts ordered17 Dec 10 CompletedConstruct and test pulse generator/transformer 31 Jan Jan 11 On trackVerify CPLD functionality6 Feb 11 On trackVerify 7-seg display and decoder functionality 6 Feb 11 On trackConstruct and test the prototype voltage multiplier. 14 Feb 11 On trackConstruct final voltage multiplier 21 Feb 11

Senior Design 7 Concerns/Issues Inexperience with CPLD’s, 555 timers, 7- segment displays and decoders could lead to delays Concerned about how much time LabVIEW will take to set up Various interfacing issues University of Portland School of Engineering

Senior Design 8 Conclusions CPLD has been created and is ready for testing before implementation into analog circuitry. We are now focused on the analog portion and having it interface with the Geiger tube. University of Portland School of Engineering

Senior Design 9 Questions? University of Portland School of Engineering