A. Yaicharoen 1 1/2551 Logic Design with MSI Circuits วัตถุประสงค์ของบทเรียน  รู้จักวงจรประเภท MSI  เข้าใจการทำงานของวงจร MSI ที่มีใช้ อยู่ทั่วไป  สามารถประยุกต์ใช้วงจร MSI ในการ ออกแบบวงจรลอจิกแบบต่างๆ ได้

A. Yaicharoen 2 1/2551 Type of Circuits หมายเหตุ หนังสือบางเล่มแบ่งวงจรที่มีเกต ตั้งแต่ 1,000,000 เกต ขึ้นไป ให้อยู่ในกลุ่ม ULSI (Ultra-large-scale integration)

A. Yaicharoen 3 1/2551 Multiplexers (MUXs) -also called a data selector Input lines consist of - data lines: 2 n lines - select lines: n lines -there may or may not be an enable line Output line: -output line: 1 line

A. Yaicharoen 4 1/2551 Multiplexer Function -Truth table of a 4:1 multiplexer (without enable) Select inputsOutput S1S1 S0S0 Y 00I0I0 01I1I1 10I2I2 11I3I3

A. Yaicharoen 5 1/2551 Multiplexer Function -Truth table of a 4:1 multiplexer (with enable) EnableSelect inputsOutput ES1S1 S0S0 Y 0XX0 100I0I0 101I1I1 110I2I2 111I3I3

A. Yaicharoen 6 1/2551 Logic Circuit Design using Multiplexer Advantages  No need for logic simplification  Minimize the IC package count  Simplify the logic design

A. Yaicharoen 7 1/2551 Logic Design using MUX Case 1: Number of inputs is equal to number of select lines Design procedure  Identify the decimal number corresponding to each minterm in the expression  Connect logic 1 level to input lines corresponding to these numbers  Connect logic 0 level to the others  Connect inputs to selected lines

A. Yaicharoen 8 1/2551 a three-variable function using a 8-to-1-line multiplexer Case1: Inputs = Select lines

A. Yaicharoen 9 1/2551 f(x,y,z) =  m(0,2,3,5) using 8-to-1-line multiplexer Example

A. Yaicharoen 10 1/2551 Logic Design using MUX Case 2: Number of inputs is higher than number of select lines Procedure 2.1: Reduce the number of inputs to the number of select lines by inspection k-map

A. Yaicharoen 11 1/2551 Case 2 -Truth table of a 3 variable logic circuit InputOutput xyzY 000f0f0 010f2f2 100f4f4 110f6f6 InputOutput xyzY 001f1f1 011f3f3 101f5f5 111f7f7

A. Yaicharoen 12 1/2551 a 3-variable Boolean function using a 4-to-1-line multiplexer Case2.1: Reducing Inputs

A. Yaicharoen 13 1/2551 f(x,y,z) =  m(0,2,3,5) using a 4-to-1-line multiplexer Example

A. Yaicharoen 14 1/2551 Reducing Inputs with K-map

A. Yaicharoen 15 1/2551 f(x,y,z) =  m(0,2,3,5) Example

A. Yaicharoen 16 1/2551 (a) Applying input variables y and z to the S 1 and S 0 select lines. (b) Applying input variables x and y to the S 0 and S 1 select lines. More on Reducing Inputs

A. Yaicharoen 17 1/2551 f(x,y,z) =  m(0,2,3,5) (a) Applying input variables y and z to the S 1 and S 0 select lines. (b) Applying input variables x and y to the S 0 and S 1 select lines. Example

A. Yaicharoen 18 1/2551 Reducing 4-input to 3-input

A. Yaicharoen 19 1/2551 f(w,x,y,z) =  m(0,1,5,6,7,9,12,15) Example

A. Yaicharoen 20 1/2551 Logic Design using MUX Procedure 2.2: Use multiplexer tree when number of inputs exceeds the largest number of inputs on available ICs Can be done by one of these two techniques -connect the MSB input to the enable/strobe input -connect the MSB input to another multiplexer

A. Yaicharoen 21 1/2551 Demultiplexers/Decoders -Performs the reverse operation of a multiplexer Input lines are: - 1 data line - n select lines - maybe 1 enable Output lines are - 2 n output lines

A. Yaicharoen 22 1/2551 A multiplexer/demultiplexer arrangement for information transmission Application Example

A. Yaicharoen 23 1/2551 Decoders A n-to-2 n -line decoder is a circuit that only one of the output line responds to the n-input data. Number of input:output is n:2 n (Note: a demultiplexer is a decoder with an enable input acting as a data input line A BCD to 7-segment decoder is a circuit that 7-bit output will make each segment of the 7-segment lit according to the 4-bit input

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A. Yaicharoen 26 1/ to-8-line Decoder

A. Yaicharoen 27 1/2551 การใช้ 3-to-8-line decoder และ or- gate ในการสร้างวงจร f1(x2,x1,x0) =  m(1,2,4,5) และ f2(x2,x1,x0) =  m(1,5,7) Application Example

A. Yaicharoen 28 1/2551 f 1 (x 2,x 1,x 0 ) =  m(0,1,3,4,5,6) =  m(2,7) and f 2 (x 2,x 1,x 0 ) =  m(1,2,3,4,6) =  m(0,5,7) Application Example

A. Yaicharoen 29 1/2551 f 1 (x 2,x 1,x 0 ) =  M(0,1,3,5) and f 2 (x 2,x 1,x 0 ) =  M(1,3,6,7) (a) Using output or-gates. (b) Using output nor-gates. Application Example

A. Yaicharoen 30 1/ to-8-line decoder using nand-gates

A. Yaicharoen 31 1/2551 f 1 (x 2,x 1,x 0 ) =  m(0,2,6,7) and f 2 (x 2,x 1,x 0 ) =  m(3,5,6,7) (a) Using output and-gates. (b) Using output nand-gates. Application Example

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A. Yaicharoen 36 1/2551 And-gate 2-to-4-line decoder with an enable input Decoder with Enable Input

A. Yaicharoen 37 1/2551 Encoders - Similar to decoders - Usually number of input lines are more than number of output lines Number of input:output is 2 n :n

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A. Yaicharoen 43 1/2551 Binary Adders Binary Half-Adder Binary Full-Adder

A. Yaicharoen 44 1/2551 Binary Full-Adder s i = x i '.y i '.c i +x i '.y i.c i '+x i.y i '.c i '+x i.y i.c i c i+1 = x i.y i + x i.c i + y i.c i

A. Yaicharoen 45 1/2551 Parallel Binary Adder Parallel (ripple) binary adder

A. Yaicharoen 46 1/2551 Binary Subtractor Binary Half-SubtractorBinary Full-Subtractor

A. Yaicharoen 47 1/2551 Parallel Binary Subtractor Parallel (ripple) binary subtractor

A. Yaicharoen 48 1/2551 Parallel Binary Adder/Subtractor

A. Yaicharoen 49 1/2551 Carry Look-ahead Adder From Boolean expression of the F.A. c i+1 = x i y i + (x i +y i )c i Let’s g i = x i y i (carry-generate function) andp i = (x i +y i )(carry-propagate function) c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 = g 1 + p 1 (g 0 + p 0 c 0 ) = g 1 + p 1 g 0 + p 1 p 0 c 0

A. Yaicharoen 50 1/2551 Carry Look-ahead Adder (cont.) c 3 = g 2 + p 2 c 2 = g 2 + p 2 (g 1 + p 1 g 0 + p 1 p 0 c 0 ) = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0... c i+1 = g i + p i g i-1 + p i p i-1 g i p i p i-1...p 1 g 0 + p i p i-1...p 0 c 0

A. Yaicharoen 51 1/2551 Carry Look-ahead Adder (cont.)   

A. Yaicharoen 52 1/2551 BCD Arithmetic BCD Adder  Using a 4-bit binary adder to perform two one digit BCD addition  a decimal 6 (binary ) will be added to the result if the sum output is an invalid BCD or if a carry at the MSB is 1  each BCD adder can be cascaded for adding several BCD digits

A. Yaicharoen 53 1/2551 BCD Arithmetic BCD Subtractor  Convert the subtrahend to its 9’s complement form  Add the result to the minuend  If the summation result is an invalid BCD code or if the carry from the MSB is 1, add decimal 6 (binary ) and the end around carry (EAC) to this sum  If the summation result is a valid BCD code, the result is negative and in the 9’s complement form

A. Yaicharoen 54 1/2551 Nine’s Complementer Circuit A 9’s complementer circuit is  a circuit designed to convert a decimal digit (in BCD code) to its 9’s complement  created by adding binary to the 1’s complement of the number (ignore the carry) (Proof is left as a student exercise)

A. Yaicharoen 55 1/2551 Arithmetic Logic Unit (ALU) performs arithmetic and logic operations (depends on the selected mode) Read details and example in section 6.6

A. Yaicharoen 56 1/2551 Comparators A comparator is a circuit that compares the magnitudes of two binary numbers Input: A i, B i, G i, E i, L i G i = 1 when A i-1 A i-2...A 1 A 0 > B i-1 B i-2...B 1 B 0 E i = 1 when A i-1 A i-2...A 1 A 0 = B i-1 B i-2...B 1 B 0 L i = 1 when A i-1 A i-2...A 1 A 0 < B i-1 B i-2...B 1 B 0 Output: G i+1, E i+1, L i+1 G i+1 = 1 when A i A i-1...A 1 A 0 > B i B i-1...B 1 B 0 E i+1 = 1 when A i A i-1...A 1 A 0 = B i B i-1...B 1 B 0 L i+1 = 1 when A i A i-1...A 1 A 0 < B i B i-1...B 1 B 0

A. Yaicharoen 57 1/ bit Comparator

A. Yaicharoen 58 1/2551 Other MSI Circuits Parity generators/checkers Code converters  BCD-to-binary converter  Binary-to-BCD converter Priority encoders  Decimal-to-BCD encoder  Octal-to-binary Encoder Decoder/drivers for display devices  BCD-to-decimal decoder/driver  BCD-to-7-segment decoder/driver