CSE331 W10.1Irwin&Li Fall 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Week 10 Section 1: Mary Jane Irwin ( Section 2: Feihui Li ( ) Course material on ANGEL: cms.psu.edu [ adapted from D. Patterson slides ]

CSE331 W10.2Irwin&Li Fall 2006 PSU Head’s Up  Last week’s material l Designing a MIPS single cycle datapath  This week’s material l More on single cycle datapath design and exam review -Reading assignment – PH: 5.4, B.8, C.1-C.2  Next week’s material l Multicycle MIPS datapath implementation -Reading assignment – PH: 5.5, C.3  Reminders l Final Exam is Tuesday, Dec 19, 4:40 to 6:30, 110 Business l HW 7 will be due, ~ Nov 30 (by 11:55pm) l Quiz 6 will be due, ~ Dec 4 (by 11:55pm) l Nov 27 is the late-drop deadline

CSE331 W10.3Irwin&Li Fall 2006 PSU Each MAS (microarchitectural specifications) included  Pipeline and block diagrams  Textual description of the theory of operation  Unit inputs and outputs and protocols governing data transfers  Corner cases of the design that were especially tricky  New circuits required for implementation  Notes on testing and validation The Pentium Chronicles, Colwell, pg. 82

CSE331 W10.4Irwin&Li Fall 2006 PSU Review: Creating a Datapath from the Parts  Assemble the datapath elements, add control lines as needed, and design the control path  Fetch, decode and execute each instructions in one clock cycle – single cycle design l no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., why we have a separate Instruction Memory and Data Memory) l to share datapath elements between two different instruction classes need multiplexors at the input of the shared elements with control lines to do the selection  Cycle time is determined by length of the longest path

CSE331 W10.5Irwin&Li Fall 2006 PSU Review: A Simple MIPS Datapath Design Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Read Address Instruction Memory Add PC 4 Shift left 2 Add PCSrc

CSE331 W10.6Irwin&Li Fall 2006 PSU Adding the Control  Selecting the operations to perform (ALU, Register File and Memory read/write)  Controlling the flow of data (multiplexor inputs)  Information comes from the 32 bits of the instruction I-Type: oprsrt address offset R-type: oprsrtrdfunctshamt 10  Observations l op field always in bits l addr of two registers to be read are always specified by the rs and rt fields (bits and 20-16) l base register for lw and sw always in rs (bits 25-21) l addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions l offset for beq, lw, and sw always in bits 15-0

CSE331 W10.7Irwin&Li Fall 2006 PSU (Almost) Complete Single Cycle Datapath Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr ALU ovf zero Data Memory Address Write Data Read Data MemWrite MemRead Register File Read Data 1 Read Data 2 RegWrite Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc 1 0 RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11]

CSE331 W10.8Irwin&Li Fall 2006 PSU ALU Control ALU control input Function 0000and 0001or 0010xor 0011nor 0110add 1110subtract 1111set on less than  ALU's operation based on instruction type and function code  Notice that we are using different encodings than in the book

CSE331 W10.9Irwin&Li Fall 2006 PSU ALU Control, Con’t  Controlling the ALU uses of multiple decoding levels l main control unit generates the ALUOp bits l ALU control unit generates ALUcontrol bits Instr opfunctALUOpactionALUcontrol lwxxxxxx00 swxxxxxx00 beqxxxxxx01 add add0110 subt subtract1110 and and0000 or or0001 xor xor0010 nor nor0011 slt slt1111

CSE331 W10.10Irwin&Li Fall 2006 PSU ALU Control, Con’t  Controlling the ALU uses of multiple decoding levels l main control unit generates the ALUOp bits l ALU control unit generates ALUcontrol bits Instr opfunctALUOpactionALUcontrol lwxxxxxx00 swxxxxxx00 beqxxxxxx01 add add0110 subt subtract1110 and and0000 or or0001 xor xor0010 nor nor0011 slt slt1111 add0110 add0110 subtract1110

CSE331 W10.11Irwin&Li Fall 2006 PSU ALU Control Truth Table F5F4F3F2F1F0ALU Op 1 ALU Op 0 ALU control 3 ALU control 2 ALU control 1 ALU control 0 XXXXXX XXXXXX XX XX XX XX XX XX XX  Four, 6-input truth tables

CSE331 W10.12Irwin&Li Fall 2006 PSU ALU Control Truth Table F5F4F3F2F1F0ALU Op 1 ALU Op 0 ALU control 3 ALU control 2 ALU control 1 ALU control 0 XXXXXX XXXXXX XX XX XX XX XX XX XX  Four, 6-input truth tables Our ALU m control input Add/subtMux control

CSE331 W10.13Irwin&Li Fall 2006 PSU ALU Control Logic  From the truth table can design the ALU Control logic Instr[3] Instr[2] Instr[1] Instr[0] ALUOp 1 ALUOp 0 ALUcontrol 3 ALUcontrol 2 ALUcontrol 1 ALUcontrol 0

CSE331 W10.14Irwin&Li Fall 2006 PSU (Almost) Complete Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE331 W10.15Irwin&Li Fall 2006 PSU End of First Lecture of the Week

CSE331 W10.16Irwin&Li Fall 2006 PSU Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOp R- type lw sw beq  Completely determined by the instruction opcode field l Note that a multiplexor whose control input is 0 has a definite action, even if it is not used in performing the operation

CSE331 W10.17Irwin&Li Fall 2006 PSU R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch zero

CSE331 W10.18Irwin&Li Fall 2006 PSU R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE331 W10.19Irwin&Li Fall 2006 PSU Store Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE331 W10.20Irwin&Li Fall 2006 PSU Store Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE331 W10.21Irwin&Li Fall 2006 PSU Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE331 W10.22Irwin&Li Fall 2006 PSU Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE331 W10.23Irwin&Li Fall 2006 PSU Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE331 W10.24Irwin&Li Fall 2006 PSU Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE331 W10.25Irwin&Li Fall 2006 PSU Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOp R-type lw sw X1X beq X0X  Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design

CSE331 W10.26Irwin&Li Fall 2006 PSU Control Unit Logic  From the truth table can design the Main Control logic Instr[31] Instr[30] Instr[29] Instr[28] Instr[27] Instr[26] R-type lwswbeq RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp 1 ALUOp 0

CSE331 W10.27Irwin&Li Fall 2006 PSU Review: Handling Jump Operations  Jump operation have to l replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Add PC 4 Shift left 2 Jump address J-Type: opjump target address 310

CSE331 W10.28Irwin&Li Fall 2006 PSU Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left Jump 32 Instr[25-0] 26 PC+4[31-28] 28

CSE331 W10.29Irwin&Li Fall 2006 PSU Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left Jump 32 Instr[25-0] 26 PC+4[31-28] 28

CSE331 W10.30Irwin&Li Fall 2006 PSU Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOpJump R-type lw sw X1X beq X0X j XXX000XXX1  Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design

CSE331 W10.31Irwin&Li Fall 2006 PSU Single Cycle Implementation Cycle Time  Unfortunately, though simple, the single cycle approach is not used because it is very slow  Clock cycle must have the same length for every instruction  What is the longest path (slowest instruction)?

CSE331 W10.32Irwin&Li Fall 2006 PSU Instruction Critical Paths Instr.I MemReg RdALU OpD MemReg WrTotal R- type load store beq jump  Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires) except: l Instruction and Data Memory (4 ns) l ALU and adders (2 ns) l Register File access (reads or writes) (1 ns)

CSE331 W10.33Irwin&Li Fall 2006 PSU Instruction Critical Paths Instr.I MemReg RdALU OpD MemReg WrTotal R- type load store beq jump  Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires) except: l Instruction and Data Memory (4 ns) l ALU and adders (2 ns) l Register File access (reads or writes) (1 ns)

CSE331 W10.34Irwin&Li Fall 2006 PSU Single Cycle Disadvantages & Advantages  Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instr l especially problematic for more complex instructions like floating point multiply  May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but  It is simple and easy to understand Clk lwswWaste Cycle 1Cycle 2

CSE331 W10.35Irwin&Li Fall 2006 PSU Where We are Headed  Another approach l use a “smaller” cycle time l have different instructions take different numbers of cycles l a “multicycle” datapath Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout