Oct 31 st 2007University of Utah1 Multi-Cores: Architecture/VLSI Perspective The Hardware-Software Relationship: Date or Dump?

University of Utah Embedded Applications --Spencer  From discreet cochlear implants to high-end biomedical imaging!  Multi-cores speed up performance by 50x!  Creating new application domains!

University of Utah How to use “multiple” cores? Oct 31 st Parallel programming Synchronization Deadlock Livelock Memory management

University of Utah Oct 31 st How to use “multiple” cores? Program = Communication + Computation  Global restructuring and parallelization

University of Utah Oct 31 st Structured “Communication” Lang: StreamIt, MPI Compilers: RAW, CoGenE Architecture: TRIPS, HWRT  Key: Help other levels and leverage communication

University of Utah Another Constraint? Oct 31 st Parallel programming Synchronization Deadlock Livelock Memory management Hey.. Surprise!!! Communication Scheduling

University of Utah Another Constraint? Oct 31 st Oh God!!! Communication Scheduling

University of Utah Focus of Architecture Research  Reduce the load of programmers Hardware transactional memory Aggressive pre-fetching Dynamic reconfiguration at every possible level  Keep the architectural innovations transparent to compilers or programmers Learn from the mistakes of ITANIUM ! Remember the success of OOO execution Oct 31 st

University of Utah 9 Reliability Issues --Niti  Shrinking transistor sizes & lower voltages  Increased transient faults, process variations – leakage power and frequency variations, hard errors, interconnect noise  Many-core – “Many cores” may not work reliably  Some cores will end up providing redundancy  Heterogeneous cores may be able to help  Simple in-order cores can provide redundancy at low cost  The compute power gain of many-core can get offset by reliability requirements of the system

University of Utah Oct 31 st On-Chip Sensor Networks --Nathaniel, Amlan Analog sensors everywhere! Need to monitor power, voltage droop, variation, critical paths, delays, slew rates, etc. Control system to react to changes. In multi-core, sensor network will only grow. Xeon and Itanium processors JSSC Jan 06 & 07 On-chip sensors