SLHC Meeting CERN, 21 May 2008 Presented by C.-E. Wulz Global Triggers,  TCA Technology M. Stettler, M. Hansen (CERN) C. Foudas, G. Iles (Imperial College) J. Jones (Princeton) A. Taurok, H. Bergauer, C.-E. Wulz (Vienna)

SLHC Trigger Meeting, May 2008 C. - E. Wulz2 Global Trigger Concepts for LHC and SLHC FDL GTL 128 Algo GMT PSB GCT Sync delay Sync delay REC COND  ALGO PSB Sync delay Technical Triggers FDL chip GTL COND chip GMT Optical links GCT Sync delay Sync delay SYNC Sync delay ‘Conditions’ COND chip nn Algo (and, or, not) FPGA: Standard Conditions - FPGA: DSPs (XC5V100T) - FPOA: DSP array Tracker Trigger Sync delay Prescalers & Trigger Counters Final OR Final OR COND  ALGO LHC SLHC Tracker ‘Conditions’ Prescalers & Trigger Counters Totem, Castor, ZDC, BTPX, BSC, …

SLHC Trigger Meeting, May 2008 C. - E. Wulz3 Global Trigger Concepts for LHC and SLHC Synchronize all Trigger Objects to arrive at the same time at the logic chip –2008 Version: Muons: done by GMT; Calo_objects: done by PSB; Technical Triggers: done by PSB –SLHC Version: Muons: done by GMT; Calo_objects: done by GCT ; TechTrig: done by SYNC chip Tracker: done by Tracker_Trigger Send all Trigger Objects into one chip to be able to make any correlations between them Use an FPGA to change trigger conditions as required by physics –New trigger setup: -> configure FPGA with new trigger conditions –New parameter values for same setup: –2008 Version: Load new ET and pT thresholds by software –SLHC Version: Load all values by software ( Upgrade Version) Calculate physics trigger algorithms in parallel (FPGA branch) –2008 Version: 128 Algorithms, limited by board layout, connectors and chip size –SLHC Ve rsion: Extend to ‘nn’ Algorithms <- ‘Algo’ signals inside chip (chip size will be the only restriction) Final OR mask for all Algorithm bits; Prescaler & Counter for each Algorithm –SLHC: maybe more requirements SLHC Version: –Array of DSPs for complex physics triggers C++ code -> trigger program with constant latency(!) –Each trigger object is received twice, on 2 optical links

SLHC Trigger Meeting, May 2008 C. - E. Wulz4 Input to Global Trigger Global Calorimeter Trigger (GCT): redefinition (reduction?) of trigger data 4 e/ , 4 isolatetd e/       4 e/  with ISOLATION bit 4 central jets, 4 forward jets      n jets 4 tau jets total_E T, H T  apply set of thresholds in GCT and send resulting bits to FDL chip missing_E T  “jet counts” (now towers above thr., ring   ’s) More than 4 objects per type: 5 or 6 (?)  Simulation for SLHC Global Muon Trigger (GMT): 4 muons  p   mip, iso, charge, quality  Tracker Trigger: Tracks/jets with  and   COND chips ‘Conditions’ calculated in Tracker Trigger  FDL chip

SLHC Trigger Meeting, May 2008 C. - E. Wulz5 CMS GT Standard Algorithm in FPGA: Example  Correlation TEMPLATE Missing Energy TEMPLATE Predefined VHDL code Single particle TEMPLATE Parameters ET thresholds 1,2  window 1,2 Missing Energy threshold  Correlation ieg1 ieg2 ieg3 ieg4 Find 2 out of 4 particles fulfilling all conditions IEG condition: ieg2wsc Combinatorial logic: Algorithm = ieg2wsc and MET Missing E T condition: MET ALGO bit (i) Final_OR Single particle thr2,  window2 Single particle thr2,  window2 Single particle thr2,  window2 Single particle thr2,  window2 Single particle thr1,  window1 Single particle thr1,  window1 Single particle thr1,  window1 Single particle thr1,  window1 ieg1 ieg4 ieg2 ieg3 ieg1 ieg4 ieg2 ieg3 Mask, Veto_mask prescalers Standard CONDITION chip FDL chip

SLHC Trigger Meeting, May 2008 C. - E. Wulz6 Condition chip with DSP array or RISCs DSP Condition program Trigger objects (GCT, GMT, TrackerTr…) Parameters Condition bit Parallel or tree structures DSP Trigger objects Latency  Algorithm logic in FDL chip Constraints: # of Conditions  # of DSPs # of instructions  latency limit Keep pipeline structure Latency = # of instructions Hardwired logic* *) if DSPs are implemented in FPGA XC5VFX100T: 256 DSP48E(550MHz), 4 Ethernet MAC, 3 PCIexpress end points, 16 GTX RocketIO (6.5Gb/s) 680 IO (1.25Gb/s LVDS) Condition bit OR

SLHC Trigger Meeting, May 2008 C. - E. Wulz7 Global Trigger board for SLHC 2 sets of opt. rcvers RX: Serial  parallel COND_logic or DSP array Ethernet IP L1A_daq + Serial TX LVDS FDL chip nn Algo (and, or, not) Final OR COND chip SYNC Chip DAQ chip L1A_daq + Serial TX GCT: 5... GMT: 2 Tracker: ~2.. Parallel data LVDS Ethernet IP Control CPU Control CPU Ethernet IP Trigger Counters Prescalers Spy_mem‘s & Ringbuffers Spy_mem‘s & Ringbuffers Event builder CMS - DAQ LVDS Condition bits Ethernet IO Sync circuits Condition bits CLK, BCRES,... LVDS TIMING circuits LVDS CLK, BCRES,.. Preliminary!

SLHC Trigger Meeting, May 2008 C. - E. Wulz8 Trigger system design based on Telcom developments

SLHC Trigger Meeting, May 2008 C. - E. Wulz9 ATCA standard

SLHC Trigger Meeting, May 2008 C. - E. Wulz10 ATCA connectivity

SLHC Trigger Meeting, May 2008 C. - E. Wulz11  TCA

SLHC Trigger Meeting, May 2008 C. - E. Wulz12  TCA for GCT Quiet/ MIP Bits Data processing  TCA module + custom active switching backplane Data processor card schematics have been designed (M. Stettler) and parts have been bought. The card is under layout at Los Alamos. Advanced PCB manufacturing techniques (e.g. micro-vias that penetrate several layers) are needed. Board stackup has been completed and verified with vendor. The Backplane has been designed (J. Jones + M. Stettler) but will be tested after the processor card. A  TCA crate and a commercial backplane have been bought and are already at CERN. The first prototypes are expected to arrive at CERN in Summer 2008.

SLHC Trigger Meeting, May 2008 C. - E. Wulz13 Main QM Data Processing Module Receives and transmits data via front panel optical links. On board 72x72 Cross-Point Switch allows for dynamical routing of the data either to a V5 FPGA or directly to the uTCA backplane. The module can exchange data with other modules either via the backplane or via the front panel optical links.

SLHC Trigger Meeting, May 2008 C. - E. Wulz14 Custom  TCA Backplane Instrumented with 144x144 cross-point switch for extra algorithm flexibility. Allows dynamical or static routing of the data to different Data Processing Modules.

SLHC Trigger Meeting, May 2008 C. - E. Wulz15 Routing detail

SLHC Trigger Meeting, May 2008 C. - E. Wulz16 BACKUP

SLHC Trigger Meeting, May 2008 C. - E. Wulz17 Global Trigger Crate 2008

SLHC Trigger Meeting, May 2008 C. - E. Wulz18 I/O, Hardware DSP48E Slices : add/subtract o = Z ± (X + Y +CIN) Accumulate o = o + A&B + C//concatenate Accumulate & shift Multiply Accumulate(MACC) MUX, BarrelShifter, Counter, multiply, divide, square_root, square_root of sum of squares, Parallel FIR Filters,… I/O requirements: 4 calo objects(jet, ieg,..)  64 bits/40MHz  2.56 Gbps 4 calo objects(jet, ieg,..)  64 bits/80MHz  5.12 Gbps 1.25 Gbps LVDS IO for each pin pair:  31 bits/40MHz // 15 bits/80MHz Virtex5 XC5VFX100T: 256 DSP48E(550MHz), 4 Ethernet MAC, 3 PCIexpress end points, 16 GTX RocketIO (6.5Gb/s) 680 =340 pairs IO (1.25Gb/s LVDS) Altera Stratix III EP3SE110 : for DSP+Memory applications DSP: x18 Multipliers for 550 MHz clock x18 sum_of_multipliers 56(88) LVDS 1.25Gb/s with serializer/deserializer (SERDES) programmable pre-emphasis, (RapidIO, … ) 64(96) LVDS low speed DSP block : 300 MHz; 8 mult18x18, regs, adders, subtractors, accumulators, multiplexer, … FPOA (..object arrays) 1GHz clock 256 ALU Arithmetic Logic Units 16 bit 64 MAC multiply&accumulate units 80 RF register set( 64 regs 16 bit) 2 fast serial IO links