Lecture Note on Switch Architectures

Function of Switch

Naive Way

Bus-Based Switch No buffering at input port processor (IPP) Output port processor (OPP) buffers cells Controller exchanges control message with terminals and other controller. Disadvantage: –Bus bandwidth is equal to sum of external link for non-blocking –IPPs and OPPs must operate at full bus bandwidth –Bus width increases with number of links

Centralized Bus Arbitration IPPs send requests to central arbiter Request may includes: –Priority –Waiting time –OPP destination(s) –Length of IPP queue Arbitration complexity is O(N^2) Distributed version is preferred, but may degrade throughput.

Bus Arbitration Using Rotating Daisy Chain Rotating token eliminates positional favoritism

Ring Switch Same bandwidth and complexity as bus switch Avoids capacitive loading of bus, allowing higher clock frequencies Control mechanisms –Token passing –Slotted ring with busy bit

Shared Buffer Switch Individual queues are rarely full. Shared memory needs two times of external link bandwidth Require less memory Better ability to handle burst traffic

Crossbar Switch

Output Buffering Efficient, but needs N time speed up internally.

Input Buffering Multiple packets simultaneously transmitted distinct outputs. Require sophisticated arbitration No speed up required Head-of-line blocking

Bi-partite Matching Require global information Complexity is O(N^(5/2)) Not suitable for hardware implementation May leads to starvation

Desired Arbitration Algorithms High throughput –Low backlog in each input queue –Close to 100% for each input and output Starvation free –No queue will be hold indefinitely Simple to implement

Options to Build High Performance Switches Bufferless crossbar Buffered crossbar Shared buffer

Bufferless Crossbar Centralized arbitrator is required –Arbitration complexity is O(N*N) –O(log 2 N) iterations of arbitration needed for high throughput Synchronization in all elements Single point failure: central arbitrator Complex line interface

Buffered Crossbar Simple scheduling algorithms –Ingress: O(1) –Egress: O(N) Inefficient use of memory –Memory linearly increased with number of ports

Shared Memory No central arbitrator needed Reduced memory requirements Distributed flow control Less timing constrains Simpler line card interface

Comparisons (1)

Comparison (2) Assume 10G for each port and packet size is 64 bytes.

Scaling Number of Ports Single larger switch is less expensive, more reliable, easier to maintain and offer better performance, but –O(n 2 ) complexity –Board-level buses limited by capacitive loading Port multiplexing Buffered multistage routing –Dynamic routing: Benes network –Static routing: Clos network Bufferless multistage routing –Deflection routing

Port Multiplexing High speed core can handles high speed links as well as low speed Sharing of common circuitry Reduced complexity in interconnection network Better queueing performance for bursty traffic Less fragmentation of bandwidth and memory

Dynamic Routing – Benes Network Network expanded by adding stages on left and right –2k-1 stages with d port switch elements supports d k ports Traffic distribution on first k-1 stages Routing on last k stages Internal load  external load Traffic maybe out of order: need re-sequencing

Static Routing - Clos network All traffic follows same path r  2d-1 to be strict non-blocking.

Deflection Routing

Basic Architectural Components: Forwarding Decision Forwarding Decision Forwarding Decision Forwarding Decision Forwarding Table Forwarding Table Interconnect Output Scheduling Forwarding Table

ATM Switches Direct Lookup VCI Address Memory Data (Port, VCI)

Hashing Function CRC Linked lists #1#2#3#4 #1#2 #1#2#3 Memory Search Data 48 log 2 N Associated Data Hit? Address { Ethernet Switches Hashing Advantages Simple Expected lookup time can be small Disadvantages Non-deterministic lookup time Inefficient use of memory

Per-Packet Processing in IP Routers 1. Accept packet arriving on an incoming link. 2. Lookup packet destination address in the forwarding table, to identify outgoing port(s). 3. Manipulate packet header: e.g., update header checksum. 4. Send packet to the outgoing port(s). 5. Classify and buffer packet in the queue. 6. Transmit packet onto outgoing link.

IP Router Lookup Destination Address Next Hop Link ---- DestinationNext Hop Forwarding Table Next Hop Computation Forwarding Engine Incoming Packet HEADERHEADER

payload Lookup and Forwarding Engine header Packet Router Destination Address Outgoing Port Forwarding Engine Lookup Data

Example Forwarding Table Destination IP PrefixOutgoing Port / / /197 IP prefix: 1-32 bits Prefix length

Multiple Matching / / /24 Routing lookup: Find the longest matching prefix (or the most specific route) among all prefixes that match the destination address / / / Longest matching prefix

Longest Prefix Matching Problem 2-dimensional search Prefix Length Prefix Value Performance Metrics Lookup time Storage space Update time Preprocessing time

Required Lookup Rates OC768c OC192c OC48c OC12c B packets (Mpps) Line-rate (Gbps) LineYear DRAM: ns, SRAM: 5-10 ns Mpps  33 ns

Size of Forward Table Year Number of Prefixes 10,000/year Renewed growth due to multi-homing of enterprise networks

Trees and Tries Binary Search Tree <> <><> log 2 N N entries Binary Search Trie

Typical Profile of Forward Table Prefix Length Number Most prefixes are 24-bits or shorter

Basic Architectural Components: Interconnect Forwarding Decision Forwarding Decision Forwarding Decision Forwarding Table Forwarding Table Interconnect Output Scheduling Forwarding Table

First-Generation Routers CPU Buffer Memory Line Interface DMA MAC Line Interface DMA MAC Line Interface DMA MAC

Second-Generation Routers CPU Buffer Memory Line Card DMA MAC LocalBufferMemory Line Card DMA MAC LocalBufferMemory Line Card DMA MAC LocalBufferMemory

Third-Generation Routers Line Card MAC Local Buffer Memory CPU Card Line Card MAC Local Buffer Memory

Switching Goals

Circuit Switches A switch that can handle N calls has N logical inputs and N logical outputs –N up to 200,000 Moves 8-bit samples from an input to an output port –Samples have no headers –Destination of sample depends on time at which it arrives at the switch In practice, input trunks are multiplexed –Multiplexed trunks carry frames, i.e., set of samples Extract samples from frame, and depending on position in frame, switch to output –each incoming sample has to get to the right output line and the right slot in the output frame

Blocking in Circuit Switches Can’t find a path from input to output Internal blocking –slot in output frame exists, but no path Output blocking –no slot in output frame is available

Time Division Switching Time division switching interchanges sample position within a frame: time slot interchange (TSI)

Scaling Issues with TSI

Space Division Switching Each sample takes a different path through the switch, depending on its destination

Time Space Switching

Time Space Time Switching

Packet Switches In a circuit switch, path of a sample is determined at time of connection establishment. No need for header. In a packet switch, packets carry a destination field or label. Need to look up destination port on-the-fly. –Datagram switches: lookup based on destination address –Label switches: lookup based on labels

Blocking in Packet Switches Can have both internal and output blocking Internal –no path to output Output –trunk unavailable Unlike a circuit switch, cannot predict if packets will block. If packet is blocked, must buffer or drop

Dealing with Blocking in Packet Switches Over-provisioning –internal links much faster than inputs Buffers –at input or output Backpressure –if switch fabric doesn’t have buffers, prevent packet from entering until path is available Parallel switch fabrics –increases effective switching capacity

Basic Architectural Components: Queuing, Classification Forwarding Decision Forwarding Decision Forwarding Decision Forwarding Table Forwarding Table Interconnect Output Scheduling Forwarding Table

Techniques in Queuing Input Queueing Output Queueing

Individual Output QueuesCentralized Shared Memory Memory b/w = (N+1).R 1 2 N Memory b/w = 2N.R 1 2 N

Input Queuing

Input Queueing Performance Delay Load 58.6% 100%

Virtual Output Queues at Input Delay Load 100%

Classification Action ---- PredicateAction Classifier (Policy Database) Packet Classification Forwarding Engine Incoming Packet HEADERHEADER

Multi-Field Packet Classification Given a classifier with N rules, find the action associated with the highest priority rule matching an incoming packet.