Figure 10.1 Cross-NOR S-R flip-flop: (a) Set condition; (b) Reset condition.
Figure 10.2 Cross-NAND S-R flip-flop.
Figure 10.3 Symbols for an S-R flip-flop.
Figure 10.4 S-R flip-flop connections using a 7402 TTL IC.
Example 10.1
Figure 10.8 Gated S-R flip-flop.
Figure 10.9 Function table and symbol for the gated S-R flip-flop of Figure 10–8.
Figure 10.7 S-R flip-flop used as a storage register.
Example 10.2
Example 10.3
Figure Gated D flip-flop.
Example 10.4
Figure The 7475 quad bistable D latch: (a) logic symbol; (b) pin configuration.
Example 10.5
Figure The 7474 dual D flip-flop: (a) logic symbol; (b) pin configuration.
Figure Positive edge-detection circuit and waveforms.