CEC 220 Digital Circuit Design Monday, August 24 CEC 220 Digital Circuit Design Slide 1 of 13

Course Outline Monday, August 24 CEC 220 Digital Circuit Design Course Web Page:  mercury.pr.erau.edu/~bruders mercury.pr.erau.edu/~bruders  Canvas Canvas o Please set the Time Zone in CANVAS to Arizona (NOT EASTERN TIME ZONE) in two places (go to Settings): – First when you first enter CANVAS, and then for each course Required Textbook:  Fundamentals of Logic Design, 7th Edition by Charles H. Roth and Larry L. Kinney Fundamentals of Logic Design, 7th Edition  Software provided by CD in textbook: o LogicAid: Manipulating logic functions o SimUaid: Graphical simulation of digital circuits o DirectVHDL: A VHDL editor and compiler Slide 2 of 13

Course Outline Monday, August 24 CEC 220 Digital Circuit Design Lectures: (Section 01)  When: M/W/F 9:00 a.m. – 9:50 a.m.  Where: KEC Rm 131 Office hours: Office hours  When: M/W/F 10 am – 11 am & M/W 3 pm – 4 pm  Where: KEC Rm 108 Help Session:  When: Monday 4 pm – 5 pm  Where: KEC Rm 130 Slide 3 of 13

Course Outline Monday, August 24 CEC 220 Digital Circuit Design Instructor:  Dr. Stephen Bruder Dr. Stephen Bruder  Office: King Eng. Center Rm. 108  Teaching Assistants (graders):  Emily Davy:  Lauren Kruszewski: Slide 4 of 13

Course Outline Monday, August 24 CEC 220 Digital Circuit Design Course Description  Introduction to logic design and interfacing digital circuits. Boolean algebra, combinatorial logic circuits, digital multiplexers, circuit minimization techniques, flip-flop storage elements, shift registers, counting devices, and sequential logic circuits. Slide 5 of 13

Course Outline Monday, August 24 CEC 220 Digital Circuit Design Course Description  Combinational Digital Logic o Number systems o Binary arithmetic o Logic gates o Logic operations o Arithmetic operations o MSI components (Encoders, decoders, MUX,...) Slide 6 of 13

Course Outline Monday, August 24 CEC 220 Digital Circuit Design Course Description  Sequential Digital Logic o Flip-Flops o State machines o State diagrams o Timing o Registers, shifters, and counters o Basic control unit  Introduction to VHDL o A basic introduction to hardware definition languages (specifically VHDL) o VHDL design of Combinational & Sequential Circuits Slide 7 of 13

Course Outline Monday, August 24 CEC 220 Digital Circuit Design Grading Scheme  Twelve Homework Assignments: 25% Twelve Homework Assignments o Your lowest hwk grade will be dropped o Must show work – Providing only the answer is insufficient!! o Homework assignments may include an optional BONUS QUESTION o Example of a hwk assignment (assignment #1)assignment #1 – Be sure to print and staple the fist page of the assignment to your hwk submission – Engineering paper may help with neatness, however, it is not manditory o The work you submit MUST be your own!! Slide 8 of 13

Course Outline Monday, August 24 CEC 220 Digital Circuit Design Grading Scheme  Three Mid-Term Exams: 15% each (total 45%) Three Mid-Term Exams o A single 8.5” X 11” cheat-sheet will be allowed in exams o No notes, no textbook, no computers  Final Exam: 30% o Date/Time: Tue, Dec 8 o A single 8.5” X 11” cheat-sheet will be allowed in exams o No notes, no textbook, no computers o Potential exemption??? All Exams will be cumulative!!! Slide 9 of 13

Course Outline Monday, August 24 CEC 220 Digital Circuit Design Class Schedule  Reading assignments for each lecture  Schedule is subject to change Slide 10 of 13

Introduction to Digital Logic: What is Digital Logic? What is Digital Logic?  The basis for all digital systems!! Monday, August 24 CEC 220 Digital Circuit Design (Intel) ? For Example Computers Slide 11 of 13

Introduction to Digital Logic: Monday, August 24 CEC 220 Digital Circuit Design Moore’s Law  Chip complexity ~doubles every two years beloit.edu Xilinx FPGA: Virtex-Ultrascale XCVU440 has > 20 billion transistors Slide 12 of 13

Introduction to Digital Logic: Monday, August 24 CEC 220 Digital Circuit Design Top 30 Innovations over the last 30 years 18 of these are tied to Digital logic Slide 13 of 13