Logical Effort of Higher Valency Adders David Harris Harvey Mudd College November 2004.

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Presentation transcript:

Logical Effort of Higher Valency Adders David Harris Harvey Mudd College November 2004

Logical Effort of Higher Valency AddersSlide 2 Outline  Are higher valency adders worth the hassle?  Prefix networks  Building blocks  Critical paths  Results  Conclusions

Logical Effort of Higher Valency AddersSlide 3 Prefix Networks

Logical Effort of Higher Valency AddersSlide 4 Pre/post computation CellTerm Noninverting CMOSInverting CMOSFooted DominoFootless Domino BitwiseLE bit 9/3 6/3 * 5/64/3 * 5/6 PD bit 6/3 + 16/37/3 + 5/65/3 + 5/6 Sum XORLE xor 9/3 3/3 * 5/62/3 * 5/6 PD xor 9/3 + 12/3 7/3 + 5/65/3 + 5/6 BufferLE buf 1 * 1/2 2/3 * 5/6 * 1/21/3 * 5/6 * 1/2

Logical Effort of Higher Valency AddersSlide 5 Valency 2 Networks

Logical Effort of Higher Valency AddersSlide 6 Valency 3: BK

Logical Effort of Higher Valency AddersSlide 7 Valency 3: LF

Logical Effort of Higher Valency AddersSlide 8 Valency 3: Sklansky

Logical Effort of Higher Valency AddersSlide 9 Valency 3: KS

Logical Effort of Higher Valency AddersSlide 10 Valency 3: HC

Logical Effort of Higher Valency AddersSlide 11 Building Blocks  Black Cells, Gray Cells, Buffers –Black cells compute G and P –Gray cells compute G  Circuit families –Inverting Static CMOS –Noninverting Static CMOS –Footed Domino –Footless Domino

Logical Effort of Higher Valency AddersSlide 12 Valency 2

Logical Effort of Higher Valency AddersSlide 13 Valency 4

Logical Effort of Higher Valency AddersSlide 14 Delay Parameters (v=2) TermCellInverting CMOS Noninverting CMOS Footed Domino Footless Domino PDg7/37/3 + 16/3 + 5/64/3 + 5/6 PDp /3 + 5/62/3 + 5/6 LEg15/31/2 * 5/61/3 * 5/6 LEg06/33/3 * 5/62/3 * 5/6 LEp1Gray6/33/3 * 5/62/3 * 5/6 LEp1Black10/36/3 * 5/64/3 * 5/6 LEp0Black4/33/3 * 5/62/3 * 5/6s

Logical Effort of Higher Valency AddersSlide 15 Delay Parameters (v=3) TermCellInverting CMOS Noninverting CMOS Footed Domino Footless Domino PDg13/313/ /3 + 5/67/3 + 5/6 PDp /3 + 5/63/3 + 5/6 LEg27/34/9 * 5/61/3 * 5/6 LEg18/32/3 * 5/61/2 * 5/6 LEg09/34/3 * 5/63/3 * 5/6 LEp2Gray5/34/3 * 5/63/3 * 5/6 LEp1Gray9/34/3 * 5/63/3 * 5/6 LEp2Black10/38/3 * 5/66/3 * 5/6 LEp1Black14/38/3 * 5/66/3 * 5/6 LEp0Black5/34/3 * 5/63/3 * 5/6

Logical Effort of Higher Valency AddersSlide 16 Delay Parameters (v=4) TermCellInverting CMOS Noninverting CMOS Footed Domino Footless Domino PDg17/317/ /3 + 5/610/3 + 5/6 PDp /3 + 5/64/3 + 5/6 LEg39/35/12 * 5/61/3 * 5/6 LEg210/35/9 * 5/64/9 * 5/6 LEg110/35/6 * 5/62/3 * 5/6 LEg012/35/3 * 5/64/3 * 5/6 LEp3Gray8/35/3 * 5/64/3 * 5/6 LEp2Gray6/35/3 * 5/64/3 * 5/6 LEp1Gray12/35/3 * 5/64/3 * 5/6 LEp3Black14/310/3 * 5/68/3 * 5/6 LEp2Black12/310/3 * 5/68/3 * 5/6 LEp1Black18/310/3 * 5/68/3 * 5/6 LEp0Black6/35/3 * 5/64/3 * 5/6

Logical Effort of Higher Valency AddersSlide 17 Wire Capacitance  Wires contribute capacitance per length –Count tracks t spanned by each wire   = (wire cap / track) / unit inverter capacitance  w =  t  W = sum(w i )

Logical Effort of Higher Valency AddersSlide 18 Delay Estimation  Ideally choose best size for each gate –Only valid if wire parasitics are negligible  Alternatively, make each stage have unit drive  How much performance does this cost? –Very little unless stage efforts are nonuniform –Overestimates delay of Sklansky / LF networks

Logical Effort of Higher Valency AddersSlide 19 Method  Create MATLAB models of adders –For each stage, list f, p, t Depends on architecture, valency, circuit family –Use MATLAB to calculate total delays  Compare ideal and unit drive delays for  = 0 –Verifies unit drive simplification  Plot D vs. # of bits

Logical Effort of Higher Valency AddersSlide 20 Results

Logical Effort of Higher Valency AddersSlide 21 Conclusions  For fast prefix networks, the logical effort model predicts that valency barely affects delay –Valency 2 designs are simpler –But most commercial designs use valency 4  Weaknesses of logical effort model –Overpredicts g for higher valency –Underpredicts p for higher valeny –Calibrate model through simulation –Or simulate entire designs