Class Report 林常仁 Low Power Design: System and Algorithm Levels.

Slides:

Advertisements

Similar presentations

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

Advertisements

Gregory Shklover, Ben Emanuel Intel Corporation MATAM, Haifa 31015, Israel Simultaneous Clock and Data Gate Sizing Algorithm with Common Global Objective.

VADA Lab.SungKyunKwan Univ. 1 L3: Lower Power Design Overview (2) 성균관대학교 조 준 동 교수

Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique Mohab Anis, Shawki Areibi *, Mohamed Mahmoud.

Keeping Hot Chips Cool Ruchir Puri, Leon Stok, Subhrajit Bhattacharya IBM T.J. Watson Research Center Yorktown Heights, NY Circuits R-US.

Power Reduction Techniques For Microprocessor Systems

L27:Lower Power Algorithm for Multimedia Systems 성균관대학교 조 준 동

S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 14: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

Spring 07, Feb 20 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Reducing Power through Multicore Parallelism Vishwani.

Dec. 6, 2005ELEC Glitch Power1 Low power design: Insert delays to eliminate glitches Yijing Chen Dec.6, 2005 Auburn university.

Spring 07, Jan 16 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.

Power Efficient Rapid System Prototyping Using CoDeL: The 2D DWT Using Lifting Nainesh Agarwal & Nikitas Dimopoulos University of Victoria, Canada PacRim,

Institute of Digital and Computer Systems 1 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Chapter 5 Finding Peak Performance in a Process.

Micro-Architecture Techniques for Sensor Network Processors Amir Javidi EECS 598 Feb 25, 2010.

2/8/06D&T Seminar1 Multi-Core Parallelism for Low- Power Design Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

Low-voltage techniques Mohammad Sharifkhani. Reading Text Book I, Chapter 4 Text Book II, Section 11.7.

Power-aware Computing n Dramatic increases in computer power consumption: » Some processors now draw more than 100 watts » Memory power consumption is.

Low Power Design of Integrated Systems Assoc. Prof. Dimitrios Soudris

Power, Energy and Delay Static CMOS is an attractive design style because of its good noise margins, ideal voltage transfer characteristics, full logic.

Mixed Logic Circuit Design

Low power architecture and HDL coding practices for on-board hardware applications Kaushal D. Buch ASIC Engineer, eInfochips Ltd., Ahmedabad, India

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

6.893: Advanced VLSI Computer Architecture, September 28, 2000, Lecture 4, Slide 1. © Krste Asanovic Krste Asanovic

EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.

04/26/05 Anthony Singh, Carleton University, MCML - Fixed Point - Integer Divider Presentation #2 High-Speed Low Power VLSI – Prof. Shams By Anthony.

ENGG 6090 Topic Review1 How to reduce the power dissipation? Switching Activity Switched Capacitance Voltage Scaling.

Tehran University Faculty of Engineering VLSI Course Class Presentation Fall 1383 Professor: DR Fakhraei Presenter: Nasim Hajary.

Power Saving at Architectural Level Xiao Xing March 7, 2005.

1 VLSI Design SMD154 LOW-POWER DESIGN Magnus Eriksson & Simon Olsson.

Determining the Optimal Process Technology for Performance- Constrained Circuits Michael Boyer & Sudeep Ghosh ECE 563: Introduction to VLSI December 5.

Low-Power Wireless Sensor Networks

TEMPLATE DESIGN © Gate-Diffusion Input (GDI) Technique for Low Power CMOS Logic Circuits Design Yerkebulan Saparov, Aktanberdi.

Logic Synthesis for Low Power(CHAPTER 6) 6.1 Introduction 6.2 Power Estimation Techniques 6.3 Power Minimization Techniques 6.4 Summary.

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

Low Power Architecture and Implementation of Multicore Design Khushboo Sheth, Kyungseok Kim Fan Wang, Siddharth Dantu ELEC6270 Low Power Design of Electronic.

Section 10: Advanced Topics 1 M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi.

CMOS Design Methods.

Washington State University

A Single Capacitor Bootstrapped Power Efficient CMOS Driver José C. García, Juan A. Montiel–Nelson Institute for Applied Microelectronics, Department of.

ELEC692/04 course_des 1 ELEC 692 Special Topic VLSI Signal Processing Architecture Fall 2004 Chi-ying Tsui Department of Electrical and Electronic Engineering.

Adiabatic Logic as Low-Power Design Technique Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams Mar. 02, 2005.

L28:Lower Power Algorithm for Multimedia Systems(2) 성균관대학교 조 준 동

DESIGN OF LOW POWER CURRENT-MODE FLASH ADC

XIAOYU HU AANCHAL GUPTA Multi Threshold Technique for High Speed and Low Power Consumption CMOS Circuits.

Radix-2 2 Based Low Power Reconfigurable FFT Processor Presented by Cheng-Chien Wu, Master Student of CSIE,CCU 1 Author: Gin-Der Wu and Yi-Ming Liu Department.

Area: VLSI Signal Processing.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Under-Graduate Project Improving Timing, Area, and Power Speaker: 黃乃珊 Adviser: Prof.

경종민 Low-Power Design for Embedded Processor.

Folding Technique: Compromising in Special Purpose Hardware Design

LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGA Project Guide: Smt. Latha Dept of E & C JSSATE, Bangalore. From: N GURURAJ M-Tech,

FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR Topics n Low power design. n Pipelining.

Class Report 何昭毅 : Voltage Scaling. Source of CMOS Power Consumption  Dynamic power consumption  Short circuit power consumption  Leakage power consumption.

VADA Lab.SungKyunKwan Univ. 1 L5:Lower Power Architecture Design 성균관대학교 조 준 동 교수

L9 : Low Power DSP Jun-Dong Cho SungKyunKwan Univ. Dept. of ECE, Vada Lab.

University of Toronto,Toronto, Ontario, Canada 1 Circuit Research Labs, Intel Corporation, Hillsboro, OR Variations-Aware Low-Power Design with Voltage.

CS203 – Advanced Computer Architecture

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Design Technologies.

LOW POWER DESIGN METHODS

M V Ganeswara Rao Associate Professor Dept. of ECE Shri Vishnu Engineering College for Women Bhimavaram Hardware Architecture of Low-Power ALU using Clock.

Adiabatic Technique for Energy Efficient Logic Circuits Design

1 VLSI Algorithm & Computing Structures Chapter 1. Introduction to DSP Systems Younglok Kim Dept. of Electrical Engineering Sogang University Spring 2007.

CS203 – Advanced Computer Architecture

LOW POWER DESIGN METHODS V.ANANDI ASST.PROF,E&C MSRIT,BANGALORE.

SECTIONS 1-7 By Astha Chawla

Low Power Design in VLSI

Circuit Design Techniques for Low Power DSPs

Jun Chen and Changbo Long

Presentation transcript:

Class Report 林常仁 Low Power Design: System and Algorithm Levels

Why Low Power Battery life in portable systems Packaging and cooling cost Digital noise immunity Power supply rail design Environmental concerns Goal: reduce power dissipations but maintaining adequate throughput rate

Low Power Design Approaches System: Hardware-software partitioning, power distribution Algorithms: Complexity, concurrency, locality, regularity, data representation Architecture: Parallelism, pipelined, signal correlations Circuit/Logic: Size, logic design, logic style Technology: Scaling, threshold reduction, advanced packaging Run at minimum allowable voltage Reduce effective switching capacitance per sample

Level of Power Reduction Level of Abstraction Expected Saving Algorithm10–99% Architecture10-90% Logic Level20-40% Layout Level10-30% Device Level10-30% General Purpose Applicable Increasing Leverage

System Level Optimization System partition is very important for low power implementation of time-slicing OFDM receiver or system-on-chip (SOC) application Energy consumption determines the battery life. Functions are implemented in different modes: -- Active modes with different clocks (voltage) -- Standby mode with slow clock -- Sleep or suspend mode (slowest clock or shut down)

Power Reduction by Clock Gating Module Unit 1 Enable 1 Module Unit 2 Enable 2 Module Unit N Enable 2 Clock   Need circuit in standby mode or active mode to generate enable signals  Modules will be partitioned by -- application functions -- speed of implementation  In SOC applications, the global clock might activate the local clock generator  Reducing power consumption can use a global synchronous local synchronous (GALS) design style

Stopping Clock of Unused Block Function A Function B Function A Function B 0 1

Algorithm Level Optimization Apply fast algorithm to reduce the average switched capacitance C L per sample Multiplies are traded-off with adds Can be combined with other low area/power techniques via voltage scaling Select the suitable algorithm to meet the requirements and to reduce the computations Algorithm transforms: parallel/pipelined processing, look ahead, retiming, folding, unfolding, strength reduction

Algorithm Optimization - Example x0x0 x1x1 x1x1 x2x2 h0h0 h1h1 h0h0 h1h1 h0h0 h 1 -h 0 h1h1 y0y0 y1y1 y0y0 y1y1 x 0 +x 1 x 1 +x 2 x1x1 4 multipliers, 2 adds3 multipliers, 5 adds  Winograd’s algorithm reduce the number of multiplies at the price of the number of adds

Precomputation-Based Optimization Comparator A > B A(n-1) B(n-1) B(n-2) A(n-2) B(0) A(0) Load Disable When A(n-1)  B(n-1)  Achieve up to 75% power reduction with 3% area overhead  In the worst case, there are an additional 1 to 5 more gate delay

Don’t Care Optimization  x1x1 x2x2 x3x3 xnxn R1 h f R2  x1x1 x2x2 x3x3 xnxn R1 h f R2 LE FF

Comparison of 8X8 DCT Algorithms AlgorithmMultiplicationsAdditions Brute Force4096 Row-Column1024 Chen [CSF77] Ligtenberg [LV86] Arai [AAN88]80464 Feig [FW92]54462 Lee [CL92]112472

References A. P. Chandreakasan and R. W. Brodersen, Minimizing Power Consumption in Digital CMOS Circuits, IEEE Proceedings, pp , April M. Mehendale and S. D. Sherlekar, VLSI Synthesis of DSP Kernels, Kluwer Academic Publishers, K. K. Parhi, VLSI Digital Signal Processing Systems – Design and Implementation, John Wiley & Sons, S.S. Rofail and K. Yeo, Low-Voltage, Low-Power Digital BiCMOS Circutis, Prentice Hall, 2000.