Weekly Group Meeting Report Renjie Chen Supervisor: Shadi A. Dayeh.

Slides:

Advertisements

Similar presentations

CMOS Fabrication EMT 251.

Advertisements

COUNCIL FOR THE CENTRAL LABORATORY OF THE RESEARCH COUNCILS EAP dimple fabrication process. Process D EAP dimple using carbon powder electrodes and DRIE.

VLSI Design Lecture 2: Basic Fabrication Steps and Layout

Adhesive Bonding with SU-8

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.

Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask.

Techniques of Synthesizing Wafer-scale Graphene Zhaofu ZHANG

Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.

Top Side Conductor vacuum deposition Aluminum sputter deposit in Argon plasma CVC 601-sputter deposition tool.

MEMS Cell Adhesion Device Andrea Ho Mark Locascio Owen Loh Lapo Mori December 1, 2006.

Project Title Name : University: Guide :. Introduction Project – what is new / what are you analyzing from this work – Example: Solar cell – increase.

Zarelab Guide to Microfluidic Lithography Author: Eric Hall, 02/03/09.

ACTFEL Alternating Current Thin Film Electroluminescent Lamps.

YoHan Kim  Thin Film  Layer of material ranging from fractions of nanometer to several micro meters in thickness  Thin Film Process 

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #7. Etching  Introduction  Etching  Wet Etching  Dry Etching  Plasma Etching  Wet vs. Dry Etching  Physical.

J. Salonen, “Flip Chip Bumping Process at VTT" [presentation for GPG], 16-March-2007 Flip Chip/Bumping Process at VTT Last modified March 16, 2007 By Jaakko.

Micro-fabrication.

CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.

Fabrication of Active Matrix (STEM) Detectors

In situ TEM Study of Ni-InGaAs Solid-State Reactions Renjie Chen.

Weekly Group Meeting Report Renjie Chen Supervisor: Prof. Shadi A. Dayeh.

1 Absolute Pressure Sensors Z. Celik-Butler, D. Butler and M. Chitteboyina Nanotechnology Research and Teaching Facility University of Texas at Arlington.

Virtual NanoFab A Silicon NanoFabrication Trainer

Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.

By: Joaquin Gabriels November 24 th,  Overview of CMOS  CMOS Fabrication Process Overview  CMOS Fabrication Process  Problems with Current CMOS.

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 LECTURE 10: KEEE 4425 WEEK 8 CMOS FABRICATION PROCESS.

Weekly Group Meeting Report Renjie Chen Supervisor: Prof. Shadi A. Dayeh.

PTC Proposal Seongjin Jang September 09, Submit Application To PTC All the users should submit their process-related information to Process Technology.

NanoFab Trainer Nick Reeder June 28, 2012.

Weekly Group Meeting Report

Etching of Organo-Siloxane Thin Layer by Thermal and Chemical Methods

Substitute beer and pizza?. Basic Silicon Solar Cell as fabricated in Cameron With Schematic.

Department of Chemistry , SungKyunKwan University

Optimization of T-Cell Trapping in a Microfluidic Device Group #19 Jeff Chamberlain Matt Houston Eric Kim.

Weekly Group Meeting Report Renjie Chen Supervisor: Prof. Shadi A. Dayeh.

Weekly Group Meeting Report Renjie Chen Supervisor: Prof. Shadi A. Dayeh.

Two-Dimensional Patterning of Nanoparticle Thin Films from in situ Microreactors Jonathan Dwyer Arizona Space Grant Symposium April 18,

LITHOGRAPHY IN THE TOP-DOWN PROCESS - BASICS

CMOS FABRICATION.

Weekly Report Renjie Chen. /6 Summary After Wednesday group meeting, I was trying to finish the last step EBL writing of Fin structure and do ICP dry.

Fab - Step 1 Take SOI Wafer Top view Side view Si substrate SiO2 – 2 um Si confidential.

Antenna Project in Cameron clean room Wafer preparation, conductor deposition, photolithography.

CMOS Fabrication EMT 251.

Date of download: 7/9/2016 Copyright © 2016 SPIE. All rights reserved. Schematic diagram of magnetic fields and their sensing on a tooth of an electric.

Weekly Group Meeting Report

Innovative Micromegas manufacturing with Microfabrication techniques

Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask.

Basic Planar Processes

CMOS Fabrication CMOS transistors are fabricated on silicon wafer

Etching Processes for Microsystems Fabrication

Mask Design for Molds.

Manufacturing Process I

Bonding interface characterization devices

ASPERA Technology Forum 20/10/2011

Weekly Group Meeting Report

Weekly Report Renjie Chen.

Summary of Samples Photolithography Samples: EBL Samples:

SCUBA-2 Detector Technology Development

Silicon Wafer cm (5’’- 8’’) mm

31/08/ GaAs and 5629 GaAs growth 5622 GaAs,

Add nitride Silicon Substrate.

Manufacturing Process I

SEM Pictures of Wafers Without Photoresist

Manufacturing Process I

Metal Assisted Chemical Etching (MacEtch)

Photolithography.

Mask Design for Molds.

Presentation transcript:

Weekly Group Meeting Report Renjie Chen Supervisor: Shadi A. Dayeh

/14 1. Ni-InGaAs Solid-state Reaction Previous Design 2 Bonding Etch InP Etch Back InP InGaAs Ni SiO 2 Si Aperture Frame HfO2HfO2 HfO 2 Remaining Problems HfO 2 InGaAs Poor HRTEM Imaging due to HfO 2 layer Membrane broken during fabrication

/143 New Design Si Directly fabricate Fins on top Deposit Ni Spin-coat PMMA Imbedded Copper TEM grids Bond to Carrier wafer With PMMA InP Lap & etch PMMA release

/144 Copper TEM Aperture Microscope image before InP etchng

/14 2. Neural Probes 5 1. Photolithography process in CINT In nano3 UCSD, the photolithography on sapphire wafer was performed with NR photoresist In CINT, there’s no NR7 resist. The resist I used, AZ-5214 for image reverse, doesn’t work well for sapphire (transparent wafer) This morning, Don helped me try the resist 5510 which gives a good resolution, however, it does not still stick to sapphire quite well. I’ll take a look at the data sheet and some literatures to modify the 5510 process.

/ Nickel silicide bonding test on Sapphire wafer 300’C 5min + 400’C 10min300’C 5min + 400’C 20min300’C 5min + 400’C 30min

/14 Thank you Q&A 7