Current Research Overview Jeremy Espenshade 09/04/08

FPGA Cluster Integration Background –Dedicated hardware coprocessors have been used extensively on certain tasks –FPGAs allow customizable hardware Changes required reconfiguring, not refabrication –Stand-alone hybrid-FPGA systems now include embedded processors and can act independently Problem –How can such a system be added to cluster and accessed just as other nodes are accessed? –How can internal FPGA hardware resources be represented externally?

FPGA Cluster Integration Master’s Thesis –Develop an MPI implementation for communication within an FPGA and between FPGAs and other compute nodes –Expected direction Embedded linux on PowerPC managing external communication for entire FPGA FSL Bus to be used within FPGA –Advisor Dr. Marcin Lukowiak, RIT Dept of Computer Engineering –Resources Virtex-II Pro, Virtex-4, Virtex-5 (ETA TBD), misc desktops

CUDA on Tesla Background –Modern GPUs have programmable shaders enabling non-graphics applications to be targetted –Nvidia supports the CUDA language for handling threads and specifying their computation –Example – Nvidia Tesla C GHz 1.5 GB 800 GHz 430 GFLOPS achievable (512 peak) Opportunity –Data parallel applications can achieve cluster-level performance on a single node

CUDA Independent Study Electronic Design Automation –Many highly parallel, very computationally intensive problems in VLSI design –Decomposable into linear algebra problems That’s what graphics cards are designed to do! –Examples Static Timing Analysis, DRC, Extraction, etc Advisor –Dr. Alan Kaminsky, RIT Dept of Computer Science Resources –Sun Microsystems Ultra 40 workstation – Red Hat Ent. Linux 4 –Dual Core 1.0 GHz AMD Opteron 2218 –8 GB RAM, 233 GB Primary, 699 GB Secondary –Tesla C870 and Quadro FX 1500