CS61C L20 Datapath © UC Regents 1 Microprocessor James Tan Adapted from D. Patterson’s CS61C Copyright 2000 UCB

CS61C L20 Datapath © UC Regents 2 Five Components of a Computer Processor (active) Computer Control Datapath Memory (passive) (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, data live when not running)

CS61C L20 Datapath © UC Regents 3 The CPU °Processor (CPU & ALU): does data manipulation and decision-making °Control: part of the processor which tells the datapath what needs to be done

CS61C L20 Datapath © UC Regents 4 Stages of the Machine Cycle °Problem: a single, atomic block which “executes an instruction” (performs all necessary operations beginning with fetching the instruction) would be too bulky and inefficient °Solution: break up the process of “executing an instruction” into stages, and then connect the stages to create the whole datapath smaller stages are easier to design easy to optimize (change) one stage without touching the others

CS61C L20 Datapath © UC Regents 5 Stages of the Machine Cycle °What general steps do they have in common? °Stage 1: Instruction Fetch no matter what the instruction, the instruction word must first be fetched from memory also, this is where we Increment PC (that is, PC = PC + 1, to point to the next instruction)

CS61C L20 Datapath © UC Regents 6 Stages of the Machine Cycle °Stage 2: Instruction Decode upon fetching the instruction, we next gather data from the fields (decode all necessary instruction data) first, read the Opcode to determine instruction type and field lengths etc (Page tells you how the instruction format may look like.)

CS61C L20 Datapath © UC Regents 7 Stages of the Machine Cycle °Stage 3: ALU Execute Take place at Arithmetic-Logic Unit the real work of most instructions is done here: arithmetic (+, -, *, /), shifting, logic (&, |), comparisons

CS61C L20 Datapath © UC Regents 8 Stages of the Machine Cycle °Stage 4: Store result in Memory the load and store instructions are done during this stage most instructions write the result of some computation into a register examples: arithmetic, logical, shifts, loads, slt what about stores, branches, jumps? -don’t write anything into a register at the end -these remain idle during this fifth stage

CS61C L20 Datapath © UC Regents 9 Generic Steps=> Machine Cycle PC instruction memory +4 rt rs rd registers ALU Data memory imm 1. Instruction Fetch 2. Decode/ Register Read 3. Execute4. Memory 5. Reg. Write

CS61C L20 Datapath © UC Regents 10 Machine Cycle (Page ) °ADD A $15, X Stage 1: Fetch this instruction from Memory and load it to Instruction Register, inc. PC Details: (PC = 0127)  Address Register: -(Address Register) = 0127 (PC) + 1  PC(new PC = 0128) -Address Register = 0127  Address Bus (Data Bus)  Data Register (Data Register)  Instruction

CS61C L20 Datapath © UC Regents 11 Machine Cycle (Page ) Compute the indexed address of the operand Fetch the Operand -(PC = 0128)  Address Register: -(PC) + 1  PC(new PC = 0129) -Address Register = 0127  Address Bus -(Address Register)  Address Bus Memory Read -(Data Bus)  Data Register -(Data Register)  one ALU Input -(Index Register)  the other ALU Input ALU ADD[ Index Register + Offset] -(Output of ALU)  Address Register Address of Operand = (Index Reg + 15) = 242A

CS61C L20 Datapath © UC Regents 12 Machine Cycle (Page ) (Address Register)=242A  Address Bus Memory Read -(Data Bus) = 1D  Data Register -(Data Register) = 1D  One ALU Input -(Accumulator A) = A1  The other ALU Input ALU ADD [1D + A1]  A = BE 16

CS61C L20 Datapath © UC Regents 13 Machine Cycle (Page 20) ADD A $15, X The time taken to execute this cycle is five MPU cycles. -1 St MPU cycle [Fetch Phase] –Fetch & Decode the first byte of the instruction. -2 nd MPU cycle [Execute Phase…] –Obtain the ‘Operand Address Field’. 2 nd byte of the instruction, and put it in it in Data Register -3 rd MPU cycle –Calculate the address of the Operand. –i.e. ADD it to Index Register

CS61C L20 Datapath © UC Regents 14 Machine Cycle (Page 20) °ADD A $15, X 4 th MPU Cycle -Get the Operand and place it in the Data Register 5 th MPU Cycle -Perform the required addition

CS61C L20 Datapath © UC Regents Programming Model of CPU (Pg 10.21) Accumulator A Accumulator B Program Counter Stack Pointer Index Register Condition Code Register -Carry Flag -Overflow Flag -Zero Flag -Negative Flag