INTRODUCTION TO INTEL X-86 FAMILY

Features of 8086 Microprocessor: Intel 8086 was launched in 1978. It was the first 16-bit microprocessor. This microprocessor had major improvement over the execution speed of 8085. It is available as 40-pin Dual-Inline-Package (DIP). It consists of 29,000 transistors.

Block Diagram of 8086

8086 CPU is divided into two independent functional parts. Execution Unit (EU) Bus Interface Unit (BIU) Flag Register General Purpose Registers Stack Pointer Register Base Pointer Registers Index Registers Queues Segment Register Instruction Pointer

Bus Interface Unit (BIU) Sends address, fetches instruction from memory Reads data from ports/memory and writes data to ports/memory. It handles transfer of data & address on buses for execution unit. Queue Segment Registers Instruction Pointer To speed up execution of program, BIU fetches 6 instruction bytes ahead of time from memory All six bytes are then held for EU in first in first out (FIFO) 6 byte register called instruction queue. Extra Segment (ES) Code Segment (CS) Stack Segment (SS) Data Segment (DS) The CS register holds 16-bit starting addr of segment, from which BIU is fetching instruction code bytes. The IP register holds 16-bit address of next code byte within code segment.

Segment Registers Additional registers called segment registers generate memory address when combined with other in microprocessor. In 8086 microprocessor, memory is divided into 4 segments as follows: Code Segment (CS): The CS register is used for addressing a memory location in the Code segment of the memory, where the executable program is stored. Data Segment (DS): The DS contains most data used by program. Data are accessed in the data Segment by an offset address or the content of other register that holds the offset address. Stack Segment (SS): SS defined the area of memory used for the stack Extra Segment (ES): ES is additional data segment that is used by some of the string to hold the destination data.

General purpose Registers Execution Unit (EU) Tells BIU where to fetch instructions or data Decodes instructions & executes them. Flag Register General purpose Registers Stack Pointer Flag is a flip-flop, which indicates some status. The 8086 has 16-bit flag register with 9 active flags. 8 general purpose registers AH, AL, BH, BL, CH, CL, DH, DL. These can be used individually for temporary storage of 8-bit data. The AL reg is called accumulator These registers in certain pairs can be used as 16-bit registers AX – 16-bit accumulator BX – base register, holds the starting base location of a memory region within a data segment CX – Counter used in loop instructions to store loop count DX – Used to contain I/O port addresses for I/O instructions The 8086 allows to set 64 KB of memory as stack.

Flag Registers of 8086 Flags Register determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. 8086 has 9 flags and they are divided into two categories: 1. Conditional Flags 2. Control Flags

Carry Flag (CF): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic. Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used internally by the processor to perform Binary to BCD conversion. Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity Flag is reset. Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset. Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set. Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF indicates that the result has exceeded the capacity of machine.

Trap Flag (TP): a. It is used for single step control. b. It allows user to execute one instruction of a program at a time for debugging. c. When trap flag is set, program can be run in single step mode. Interrupt Flag (IF): a. It is an interrupt enable/disable flag. b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. c. It can be set by executing instruction sit and can be cleared by executing CLI instruction. Direction Flag (DF): a. It is used in string operation. b. If it is set, string bytes are accessed from higher memory address to lower memory address. c. When it is reset, the string bytes are accessed from lower memory address to higher memory address.

8086 80286 80386 80486 80586/Pentium 16-bit µp (1978). Designed to be used as CPU in microcomputer systems. 16-bit data bus, 20-bit addr bus. Can address Physical memory of 1 MB. 10 MHz Least significant 8-bit addr bus is multiplexed with data bus. Words are stored in 2 consecutive bytes. If 1st byte has even addr then it can read it in single operation Support multiplication & division 16-bit µp (1982) Designed to be used as CPU in multitasking operating systems. 16-bit data bus, 24-bit addr bus Has real & protected modes of operation. Can address 1 MB in real mode, 16 MB in protected mode. 6-20 MHz Work upto 1 GB of virtual memory. Added hardware multitasking. The program written for 8086 can run on 80826. 32-bit µp (1985) 32-bit data bus, 32-bit nonmu-xed addr bus Can address Physical memory of 4GB. 25 MHz Can be operated in 2 memory management modes- Paged mode & Non-paged mode. In paged mode it switches paging unit then after the segment unit. The paging unit allows memory pages of 4 KB each to be swapped in & out from disk. Non-paged mode is similar to 80286 32-bit µp (1989) 32-bit data bus, 32-bit addr bus Can address Physical memory of 4 GB. 60 MHz It is a large integral circuit, contains a fast built in math co-processor, a (MMU) & 8KB cache memory. Has DX & SX versions. Has high speed operation from its faster clock speeds, internal pipe-lined architecture. DX2 & DX4 has double & triple clock speed resp. 64-bit µp (1993) 64-bit data bus, 36-bit addr bus Can address Physical memory of 64 GB. 100 MHz It can process more than 1 instruction per clock cycle due to a dual pipe lined processor. Both data & code cache on chip responsible for increased processing speed. Has Branch prediction. Has 64-bit data bus, so perform data transfer with double speed.

Programming model for 16-bit version of X-86 family with register set 7 0 AX AH AL Accumulator BX BH BL Base Register CX CH CL Count DX DH DL Data SI Source Index DI Destination Index BP Base Pointer SP Stack Pointer CS Code Segment SS Stack Segment DS Data Segment ES Extra Segment IP Instruction Pointer Flag Register 16-bit version includes 8088, 8086, 80286 3 register groups 1st group contains 8 general purpose registers– A, B, C, D, SI, DI, BP, SP registers. AL, BL… indicates lower bytes & AH, BH….indicates higher bytes. Full 16-bit reg are AX, BX, CX, DX where X stands for extended. SI, DI, BP, SP are 16-bit reg called pointer reg as they are used to point location within a segment. 2nd group is segment register consisting of code segment, stack segment, data segment, extra segment. This reg manages operation with external memory. Addr computation & Data movements are performed here. 3rd group contains instruction pointer & flag register. General Purpose Registers Segment Register

Programming model for 32-bit version of X-86 family 31 16 8 7 0 EAX AH AL Accumulator EBX BH BL Base Register ECX CH CL Count EDX DH DL Data ESI SI Source Index EDI DI Destination Index EBP BP Base Pointer ESP SP Stack Pointer CS Code Segment SS Stack Segment DS Data Segments ES GS FS EIP IP Instruction Pointer E Flag 32-bit version includes 80386, 80486 General Purpose Registers 3 register groups 1st group contains 8 general purpose registers– EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP registers. E tells they can have extended length. Each can be addressed in 8, 16 or 32-bit models 2nd group is segment register consisting of code segment (CS), stack segment (SS), data segment (DS) and extra segment (ES, FS, GS). This register manages operation with external memory. Addr computation & Data movements are performed here. 3rd group contains instruction pointer & flag register. Segment Register

A – Auxilliary carry flag Z – Zero flag S – Sign flag T – Trap flag 31……… 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED AC VM RF O NT IO PL D I T S Z - A P C C…. Carry flag P – Parity flag A – Auxilliary carry flag Z – Zero flag S – Sign flag T – Trap flag I – Interrupt flag D – Direction flag O – Overflow flag IO, PL – I/O Privilege level NT – Nested Task flag RF - Resume flag VM – Virtual mode flag AC – Alignment flag