Introduction to Verilog Section 3.10. Outline Set Up the Environment Your First Verilog File Set Up the Test Bench Running the Simulation.

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Presentation transcript:

Introduction to Verilog Section 3.10

Outline Set Up the Environment Your First Verilog File Set Up the Test Bench Running the Simulation

Set Up the Environment Set up the es210 library Create verilogSandBox directory

Add a New Library Pre-requisite step: 1. Start Redhat &Cadence as shown in the lab manual.

Create a verilogSandBox directory Open a terminal. Go to ~r2d2/design/cmrf7sf.V ML/es210 – cd design – cd cmrf7sf.V ML – cd es210 Create a directory called verilogSandBox – mkdir verilogSandBox

Your First Verilog Program module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule

module....endmodule module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule Always start the verilog program with the keyword pair module…endmodule The keyword module must always be terminated by the keyword endmodule.

Keywords module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule fig3p37 is the name of the module.

Semicolon module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule Each Statement is terminated with semicolon.

wire module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule Internal connection is declared with the keyword wire.

Your First Verilog Program module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule And, not or are primitive gates. The output of a primitive gate is always listed first. The inputs can be listed in any order. G1 is an instance of the and gate.

Set Up the Testbench

Test Bench Definition of the module fig3p37 is the module name. I1 is the instance of the module.

Declare A, B, C as Outputs

Test Bench (`) is a back quote. The first number specifies the unit of measurement for delays. The second number specifies the precision for which delays are rounded off.

Initial begin…end The initial keyword is used with a set of statements That begin executing when the simulation is initialized. begin….end The statements are executed in sequence from top to bottom.

Delay/Number Specification # specifies the delay in the number of time units A is one bit with a value of 1.

Running Simulation Execute the Verilog Simulation Display the waveforms Use Schematic Tracer

Execute Verilog Simulation

View Waveform Via SimVision 1: Select on fig3p37_tb 2. Ctrl+ Select Signals 3. Select waveform editor

Run Simulation 1. Click on the play button

Change the Units to ms

Zoom Out

Display Schematic 1. Select the signals with Ctrl. 2. Activate Schematic Tracer.

Move the Cursor and Observe Change in Node Values

Assignment Replace G3 with an XOR gate. Submit – A print-out of the Verilog file – A print-out (screen capture) of the SimVision Window