Branch : IT Semester : 3 PREPARED BY:- Rajpurohit Shravansingh (140463116012) Patel Dipesh (140463116007) Shah Maulin(140463116017)

Slides:



Advertisements
Similar presentations
Programmable Logic Controllers.
Advertisements

Combinational Circuits
ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices XOR, Parity Circuits, Comparators.
Combinational Circuits. Analysis Diagram Designing Combinational Circuits In general we have to do following steps: 1. Problem description 2. Input/output.
n-bit comparator using 1-bit comparator
ReturnNext A circuit that compares two binary words and indicates whether they are equal is called a comparator. Some comparators interpret their input.
EET 1131 Unit 7 Arithmetic Operations and Circuits
Lecture #9 EGR 277 – Digital Logic
Combinational Logic and Verilog. XORs and XNORs XOR.
Design of Arithmetic Circuits – Adders, Subtractors, BCD adders
DIGITAL SYSTEMS TCE OTHER COMBINATIONAL LOGIC CIRCUITS WEEK 7 AND WEEK 8 (LECTURE 1 OF 3) COMPARATORS CODE CONVERTERS.
Digital Fundamentals Floyd Chapter 6 Tenth Edition
COMBINATIONAL CIRCUITS USING TTL 74XX ICS
DIGITAL SYSTEMS TCE OTHER COMBINATIONAL LOGIC CIRCUITS DECODERS ENCODERS.
Combinational circuits
AOI Logic Implementation © 2014 Project Lead The Way, Inc.Digital Electronics.
Digital Fundamentals with PLD Programming Floyd Chapter 8
XOR, XNOR, and Binary Adders
Dr. Bernard Chen Ph.D. University of Central Arkansas
Digital Electronics.
XOR and XNOR Logic Gates. XOR Function Output Y is TRUE if input A OR input B are TRUE Exclusively, else it is FALSE. Logic Symbol  Description  Truth.
Functions of Combinational Logic
Sneha.  Gates Gates  Characteristics of gates Characteristics of gates  Basic Gates Basic Gates  AND Gate AND Gate  OR gate OR gate  NOT gate NOT.
7-6 단일 레지스터에서 Microoperation Multiplexer-Based Transfer  Register 가 서로 다른 시간에 둘 이상의 source 에서 data 를 받을 경우 If (K1=1) then (R0 ←R1) else if (K2=1) then.
1 Tutorial: ITI1100 Dewan Tanvir Ahmed SITE, UofO.
Eng. Mohammed Timraz Electronics & Communication Engineer University of Palestine Faculty of Engineering and Urban planning Software Engineering Department.
Logic Gates. The Inverter The inverter (NOT circuit) performs the operation called inversion or complementation. Standard logic symbols: 1 1 input output.
Digital Logic Design (CSNB163)
Summary Half-Adder pp302Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry.
EKT 124 / 3 DIGITAL ELEKTRONIC 1
1 Chapter 4 Combinational Logic Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables,
© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.
Designing Combinational Logic Circuits
WEEK #11 FUNCTIONS OF COMBINATIONAL LOGIC (PART 4)
Karnaugh Map and Circuit Design.
© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Binary Numbers For digital systems, the.
Lecture # 10 University of Tehran
Digital Design Module 2 Decoder Amit Kumar AP SCSE, GU Greater Noida.
The inverter performs the Boolean NOT operation. When the input is LOW, the output is HIGH; when the input is HIGH, the output is LOW. The Inverter AX.
Chapter 33 Basic Logic Gates. Objectives After completing this chapter, you will be able to: –Identify and explain the function of the basic logic gates.
Logic Design (CE1111 ) Lecture 4 (Chapter 4) Combinational Logic Prepared by Dr. Lamiaa Elshenawy 1.
Universal Gate – NOR Universal Gate - NOR Digital Electronics
Universal Gate – NAND Universal Gate - NAND Digital Electronics
Digital Fundamentals Floyd Chapter 3 Tenth Edition
EKT 124 / 3 DIGITAL ELEKTRONIC 1
Engr. Micaela Renee Bernardo
Universal Gate – NAND Universal Gate - NAND Digital Electronics
Digital Fundamentals Floyd Chapter 3 Tenth Edition
Exclusive OR Gate.
Combinational Circuit Design
Combinational Logic Circuits
Digital Fundamentals Floyd Chapter 6 Tenth Edition
Computer Architecture CST 250
XOR, XNOR, and Binary Adders
Universal Gate – NAND Universal Gate - NAND Digital Electronics
Chapter 6 Functions of Combinational Logic
Universal Gate – NOR Universal Gate - NOR Digital Electronics
King Fahd University of Petroleum and Minerals
XOR, XNOR, & Binary Adders
Universal Gate – NAND Universal Gate - NAND Digital Electronics
Digital Fundamentals Floyd Chapter 3 Tenth Edition
Logic Gates.
EE207: Digital Systems I, Semester I 2003/2004
Universal Gate – NOR Universal Gate - NOR Digital Electronics
Logic Gates.
Binary Logic.
XOR, XNOR, and Binary Adders
XOR Function Logic Symbol  Description  Truth Table 
XOR, XNOR, and Binary Adders
ECE 352 Digital System Fundamentals
Presentation transcript:

Branch : IT Semester : 3 PREPARED BY:- Rajpurohit Shravansingh ( ) Patel Dipesh ( ) Shah Maulin( )

Comparator is a combinational logic circuit that compares the magnitudes of two binary quantities to determine which one has the greater magnitude. In other word, a comparator determines the relationship of two binary quantities. A exclusive  OR gate can be used as a basic comparator.

If two input bits are not equal, its output is a 1. But if two input bits are equal, its output is a 0. So exclusive  OR gate can be used as a 2  bit Comparator.

In order to compare binary numbers containing two bits each, an additional XOR gate is necessary 2 LSB of two numbers are compared by gate G1 2 MSB of two numbers are compared by gate G2 2 Inverters and 1 AND gate can be used

Logic diagram for equality comparison of two 2-bit numbers.. XOR gate and inverter can be replaced by an XNOR symbol.

There are two different types of output relationship between the two binary quantities; Equality output indicates that the two binary numbers being compared is equal (A = B) and Inequality output that indicates which of the two binary number being compared is the larger. That is, there is an output that indicates when A is greater than B (A > B) and an output that indicates when A is less than B (A < B).

The 74LS85 compares two unsigned 4-bit binary numbers, the unsigned numbers are A 3, A 2, A 1, A 0 and B 3, B 2, B 1, B 0. Cascading Inputs Outputs

Fig : 4-bit magnitude comparator

Start with most significant bit in each number to determine the inequality of 4-bit binary numbers A and B Output A<B will be HIGH if A 3 =0, and B 3 =1 Output A>B will be HIGH if A 3 =1, and B 3 =0 If A 3 =0, and B 3 =0 or A 3 =1, and B 3 =1, then examine the next lower order bit position for an inequality.Only when all bits of A=B, output A=B will be HIGH

The general procedure used in comparator: Start with the highest-order bits (MSB) When an inequality is found, the relationship of the 2 numbers is established, and any other inequalities in lower- order positions must be ignored THE HIGHEST ORDER INDICATION MUST TAKE PRECEDENCE

Example: Determine the A=B, A>B, and A<B outputs for the input numbers shown on the 4-bit comparator as given below. Solution: The number on the A inputs is 0110 and the number on the B inputs is The A > B output is HIGH and the other outputs (A=B and A<B) are LOW

In addition, it also has three cascading inputs: These inputs provides a means for expanding the comparison operation by cascading two or more 4  bit comparator. To expand the comparator, the A B outputs of the lower  order comparator are connected to the corresponding cascading inputs of the next higher  order comparator.

The lowest-order comparator must have a HIGH on the A=B, and LOWs on the A B inputs as shown in next slide. The comparator on the left is comparing the lower-order 8  bit with the comparator on the right with higher  order 8  bit. The outputs of the lower  order bits are fed to the cascade inputs of the comparator on the right, which is comparing the high-order bits. The outputs of the high-order comparator are the final outputs that indicate the result of the 8  bit comparison.

Fig : Two 74HC85s cascaded to perform an eight bit comparator