Integration of Modelling Tools for Parallel Optical Interconnects in a Standard EDA Design Environment Michiel De Wilde, Olivier Rits, Wim Meeus, Hannes Lambrecht, Jan Van Campenhout Ghent University, Belgium IMEC Good afternoon. In this presentation I will address the modelling and integration into Design Automation tools of guided-wave parallel optical interconnects between ICs at the PCB or rack level. EDA modelling of POI with direct CMOS-optics hybridization

Overview Chip-to-chip Parallel Optical Interconnects (POI) Concept: CMOS with hybridized optics Integration in EDA tools EDA support for POI elements (IC and system level) (compared to electrical interconnect) Coherent circuit-level simulation Analog models Digital simulation Timing verification: random behaviour in POI This is the outline of my talk. First I will give you a conceptual image of the kind of optical interconnect that is addressed here, and show the different elements that play a role in the interconnect system. Then I will show how we can represent the active elements of the interconnect in EDA tools, discuss the provided design support at the IC and system design level and compare this support to the design support for electrical interconnects. I won't talk about the design of the routing of the interconnect itself, because the required support is too specific to the applied waveguide technology for the scope of this talk. I _will_ discuss analog simulation models of all interconnect building blocks that together constitute a coherent model of the parallel optical interconnect, a model that can be evaluated with a circuit simulator. I will mention how this analog modelling could be used for optimisation of the interconnect itself, and for simulation and timing verification within a digital system. For this timing verification part, just modelling the typical behaviour of the optical links doesn't suffice, you additionally need to take random effects into account , for instance to obtain jitter and skew figures. Here I will enumerate the most important stochastic effects in POI. To conclude, I will show you our measurement setup for one important noise effect, the impact of electrically coupled noise through the CMOS substrate on the bit error rate of optical links. EDA modelling of POI with direct CMOS-optics hybridization

Concept: CMOS with hybridized optics Connector Fiber bundle Package PCB This is a conceptual view of the parallel optical interconnect that is addressed here. On top of a CMOS substrate with some digital functionality, electro-optical conversion arrays are flipchipped. This assembly is put into a special package. The arrays contain vertically emitting lasers (or VCSELs) and photodiodes. The light is transported from VCSELs to photodiodes through plastic optical fiber bundles terminated with special connectors (like here) or one can use waveguides that are integrated into a PCB layer. VCSELs Photodiodes Solder balls CMOS substrate (top side visible) EDA modelling of POI with direct CMOS-optics hybridization

POI elements Driver & receiver VCSEL technology Clock re-sync circuitry Driver & receiver TX VCSEL technology Photodetector technology Connectorization Optical waveguides (POF/integrated) Optics-CMOS hybridization IC packaging These are the different elements that play a role in the presented optical interconnect system: process technology of optical devices, a method for hybridisation of CMOS with optics, a packaging approach, fiber production, routing and connectorisation or an integrated waveguide process, analog circuitry to control the optical devices and CMOS support for digital retiming. Waveguide routing technology EDA modelling of POI with direct CMOS-optics hybridization

Interconnect data flow parallel optical interconnect In a complete one-to-one optical link, the digital signal is converted into a drive current by analog CMOS circuitry. The VCSEL converts this current in an optical signal. After propagation through the optical path, a photodiode converts the light back into a current signal, which is converted into a digital voltage signal again by a transimpedance amplifier. Finally there is an optional retiming circuit. Lets compare this to a high-speed differential electrical link. There, the digital signal is converted by the LVDS driver into a loop current. This signal propagates through the package, a differential wire pair on the PCB and the destination package to a LVDS differential receiver circuit where we get a digital voltage again. The optional retiming is here just as well. electrical interconnect EDA modelling of POI with direct CMOS-optics hybridization

EDA support for interconnections For interconnect, design tools normally provide: Design (instantiation) of system-specific parts pre-production Validation post-production Testing IC level D,V & T PCB level D, V (& T) IC level D,V & T interface V interface V Which assistance are EDA tools for system designers meant to provide regarding the interconnect? We can isolate three funtions: Assistance in designing parts of the interconnect that are system-specific, and allowing choice between different options for interconnect elements Assistance in the verification of the correct operation of the interconnect together with the rest of the system before production Assistance in testing the operation of the interconnect after production. The system-specific parts requiring tool assistance are the instantiation and on-chip connection of electrical pads or optical interface circuits at the IC level and the design of the electrical and optical routing layout at the PCB or system level. I will here only discuss the IC level (you will hear of the PCB level in the next presentation). For point two, the first step is enabling analog simulation for all parts of the interconnect. I will go into analog models for each link building block that together form a coherent simulation package that is suitable for a circuit simulator. I will also consider the testing part. +pads +pads EDA modelling of POI with direct CMOS-optics hybridization

IC-level EDA support for interconnect Electrical interconnect: pads + I/O circuits (reduced) layout view analog & digital simulation views Parallel optical interconnect: VCSEL driver/photodiode receiver + flip-chip pads design kit: similar approach For electrical interconnect, a designer is able to place electrical pads with I/O buffers or high-speed driver and receiver circuits in the layout, and simulate these on an analog or digital level. Most of the time only reduced layouts of these circuits are available to the designer. For POI, the VCSEL driver and photodiode receiver circuits with flip-chip pads for the optical arrays need to be instantiated at the right location. These circuits can just as well as with electrical interconnect be delivered as a design kit containing cells for transmit and receive circuits with a reduced layout view, and analog and digital simulation views. EDA modelling of POI with direct CMOS-optics hybridization

Driver/receiver simulation model Normal analog electrical circuits IP protection: compiled/no real circuit given Alternative: parameterised flowchart Validation: comparison with compiled circuit Receiver flowchart Photocurrent input Transimpedance preamplifier Postamplifier Equalizer For analog simulation, circuit-level models for the drivers and receivers are very simple because they are real circuits and can hence be natively represented. Sadly, due to IP restrictions, the exact circuit internals are often not made public. In that case, the IP holder could distribute a non-reverse-enigeerable compiled netlist of the circuit (and thereby limit you to a specific simulation environment) or the IP provider could distribute a simplified model, consisting of interconnectible models of the main subcircuits, the behaviour of which can be described with adequate accuracy in an analog HDL. Limiting amplifier Decision circuit Digital output EDA modelling of POI with direct CMOS-optics hybridization

Post-assembly testing of optical links JTAG Boundary Scan cells in RX/TX circuits DC-free signal alternating on test clock: AC-JTAG The testing of the optical links also requires EDA support at the IC level. Electrical connections are normally tested through JTAG boundary scan cells, and there is no reason why you cannot do the same for optical interconnections. In the Interconnect by Optics project, our project partner Helix has augmented the analog driver and receiver circuits with boundary scan cells. The image shows the assembled and packaged test chip of 3 slides ago where the BGA is controlled by individual probe needles through JTAG. Note that because the optical receiver needs a DC-balanced signal, an AC extension of JTAG is used where output signals alternate on the test clock. EDA modelling of POI with direct CMOS-optics hybridization

Photonics in circuit-level simulators Verilog-AMS and VHDL-AMS support “optical power” Options at the interface between models: light power light power modelled device A modelled device B modelled device A modelled device B current-like approach potential-like approach Natural choice: current-like approach, but Kirchhoff’s first law is enforced Photons from opposite directions would counteract each other? Potential-like: explicit optical propagation inside models I will temporarily stop discussing the IC-level support here. With only the analog models for the optical driver and receiver circuits one cannot do much. For analog simulation purposes, models for the optical devices and the optical path are required as well. Now I should say something about the support for optics in circuit-level simulators. Both analog HDL languages Verilog-AMS and VHDL-AMS explicitly support analog quantities that are not voltages nor currents: you can designate quantities as representing “light power” as well. When you interconnect the external interface terminals of simulation models, you have two options: either you communicate light power from one model to the next as a potential-like quantity, yielding the same value on connected terminals, or as a current-like quantity flowing between connected terminals. Obviously the most intuitive and natural way to look at light power is as a current of photons between device terminals, the second option. However, circuit simulators always force the first law of Kirchhoff on current-like branches. This would mean that photons cannot be absorbed in media, and even worse, that light travelling in opposite directions through a fiber would cancel out. So we should use the potential-like approach and explicitly arrange for light propagation inside the model descriptions. Also note that for the bidirectional channel of a fiber, one terminal is needed for each direction. EDA modelling of POI with direct CMOS-optics hybridization

VCSEL modelling Highly nonlinear differential equation system (image: M.X. Jungo) carrier density photon number in the kth mode VCSELs are a semiconductor lasers that can be directly fabricated in 2D arrays, so they are very suited for POI. The multimode VCSEL behaviour is highly dynamic and nonlinear. The device has different modes in which light is emitted and those compete with each other. The behaviour can be described by the rate equations for the carrier density N in the cavity and photon densities S for the different modes, which are too complex to further elaborate here. For circuit-level simulation, the spatial integration is much too slow, and not possible in circuit simulators. Spatial integration is too slow (and not possible with circuit-level simulators) EDA modelling of POI with direct CMOS-optics hybridization

Verilog-AMS VCSEL model Abstractions by Mena, Morikuni, Jungo: fix the shape of mode profiles result: spatial integration becomes static in out<1:2> gnd! optical power per mode & fixed mode profiles Fortunately, Mena and Jungo have made several abstractions of the model. As a result, the spatial integration can be done statically before the simulation, and only time-domain integration is left. In this abstraction, the shape of the VCSEL mode profiles is fixed beforehand. So in the simulation model, the optical output can be described by one quantity per mode, which amounts to the light power emitted in that mode. In the Verilog-AMS implementation, there were some convergence and other numerical issues. Positive values had to be squared to eliminate negative solutions, the initial operating point had to be approximated by simplified equations and we had to scale some large quantities down to the normal range for voltages and currents to keep the simulator from panicking. Electrical model: diode + parasitics Convergence and numerical issues EDA modelling of POI with direct CMOS-optics hybridization

Photodiode modelling Linear: electrical current vs. optical power I (mA) responsivity L I dark current L (mW) The photodiode converts the optical power back into light. The behaviour is fortunately much simpler: the optical power to electrical current relationship is essentially linear. Furthermore, the intrinsic dynamics of the photodiode response are overwhelmed by the electrical parasitics, so the exact impact of photons on the photodetector does not have to be taken into account. This means that the simulation model just needs one terminal representing the total incident light power. Electrical parasitics overwhelm intrinsic response Result: only total incident light power is required EDA modelling of POI with direct CMOS-optics hybridization

Verilog-AMS photodiode model module pin_photodiode(in,anode,cathode); input in; inout anode, cathode; power in; electrical anode, cathode; parameter real Cdep=0, Cbo=0, Rbas=0, Resp=0, Id=0; parameter real pole=-1/(Cdep*Rbas); parameter real laplace_coeff_0=Cdep+Cbo; parameter real laplace_coeff_1=Cdep*Cbo*Rbas; charge rc; analog begin I(cathode,anode) <+ laplace_zp(Resp*Pwr(in)+Id,{},{pole,0}); Q(rc) <+ laplace_np(V(cathode,anode),{laplace_coeff_0,laplace_coeff_1},{pole,0}); end endmodule Terminals Model parameters Equations describing internal state and outputs Here you see what a Verilog-AMS representation looks like. It consists of three parts: the interface terminals, the differential equations describing the behaviour and a some model parameters. EDA modelling of POI with direct CMOS-optics hybridization

Parameter extraction Photodiode model: easy VCSEL model: difficult simple measurements datasheet VCSEL model: difficult nonlinearity multiple modes temperature sensitivity + self-heating many model parameters (>60 for only 2 modes) datasheet not sufficient Ideally: standardized model (~BSIM transistor model) For photodiodes, these model parameters can be extracted from real devices with only a few measurements, that you generally don’t need to make yourself because you can read them from the photodiode datasheet. For the more complex VCSEL model, however, parameter extraction from measurements is a lot more complicated because of the nonlinearity of the device, temperature sensitivity combined with self-heating, the multiple modes and the vast amount of model parameters. VCSEL datasheets generally carry values for the most interesting properties, but not enough to get any simulation model running. We are currently working on a parameter extraction approach on VCSELs. For a good integration in design tools, it would be far better that an industry standard circuit-level VCSEL model is fixed in the future, and that the device manufacturers extract and publish the parameters of their VCSELs once and for all. Then you could rapidly switch between different VCSELs for a simulation. Such kind of standardisation of model and parameter extraction approach is for instance widely accepted for the BSIM series of SPICE transistor models. EDA modelling of POI with direct CMOS-optics hybridization

Optical path Two approaches for the optical path: Routed POF Integrated waveguides Ribbonisation As mentioned earlier, we are adressing two approaches for the optical path here: either using plastic optical fiber where fibers are bundled by ribbonisation or routing on flexfoils, or an integrated approach where waveguides are constructed in a layer that is meant to be integrated into a circuit board. Routing on flexible foil EDA modelling of POI with direct CMOS-optics hybridization

Optical path model Photodiode input = S propagated VCSEL modes Categories: interface jumps & waveguides Interface jumps: During simulation, multiply with 0 < h < 1 To calculate h (statically): Fresnel diffraction of free-space propagation For the circuit-level modelling of the optical path, we can treat the propagation of the different VCSEL modes individually for each mode throughout the optical path, and add the contributions at the photodiode inputs. The optical path can be split up in two parts: interface changes---between waveguides and other waveguids or optical devices---and propagation through waveguides. The interface jumps are couplings between a waveguide and an optical device or another waveguide. This can be modelled by a coupling efficiency factor. This factor can be calculated statically before simulation where free-space propagation of a mode profiles is calculated by solving the near-field Fresnel diffraction formulas. EDA modelling of POI with direct CMOS-optics hybridization

Optical misalignment VCSEL-POF coupling efficiency VCSEL diameter: 8µm, fiber core: 50µm VCSEL-POF distance (µm) Misalignment: 0µm Misalignment: 10µm Numerical aperture of POF EDA modelling of POI with direct CMOS-optics hybridization

Propagation in waveguides Multimode: apply raytracing Transmission of a step index POF after a 90° bend (input pattern: far field of VCSEL) Core diameter: 50µm Core diameter: 98µm Bending radius (µm) Numerical aperture of POF EDA modelling of POI with direct CMOS-optics hybridization

Dispersion in waveguides POF with graded index: ~0.1ps for 1m light travels faster nearby the cladding  Dispersion is negligible here step index POF/PCB integrated: ~100ps for 1m  Dispersion cannot be neglected anymore EDA modelling of POI with direct CMOS-optics hybridization

Coherent interconnect simulation (exaggerated VCSEL model parameters) EDA modelling of POI with direct CMOS-optics hybridization

POI simulation within a digital system Digital views with just signal propagation Cell with multiple views: interface correspondence vcc! in in out out<1:N> gnd! gnd! propagate over fundamental mode Extract delays from analog simulation and annotate to digital model using SDF files Timing verification: minimal/maximal timings required… EDA modelling of POI with direct CMOS-optics hybridization

Random effects in POI Static deviations Coupled noise Manufacturing process fluctuations Mechanical tolerances Random noise processes VCSEL relative intensity & phase noise Receiver circuit: thermal noise Coupled noise Optical crosstalk Supply noise Substrate noise EDA modelling of POI with direct CMOS-optics hybridization

Acknowledgements IST Interconnect by Optics project partners Fund for Scientific Research – Flanders (Belgium) (F.W.O.) Research assistantship EDA modelling of POI with direct CMOS-optics hybridization

Summary Chip-to-chip Parallel Optical Interconnects (POI) Concept: CMOS with hybridized optics Integration in EDA tools EDA support for POI elements (IC and system level) (compared to electrical interconnect) Coherent circuit-level simulation Analog models Digital simulation Timing verification: random behaviour in POI This is the outline of my talk. First I will give you a conceptual image of the kind of optical interconnect that is addressed here, and show the different elements that play a role in the interconnect system. Then I will show how we can represent the active elements of the interconnect in EDA tools, discuss the provided design support at the IC and system design level and compare this support to the design support for electrical interconnects. I won't talk about the design of the routing of the interconnect itself, because the required support is too specific to the applied waveguide technology for the scope of this talk. I _will_ discuss analog simulation models of all interconnect building blocks that together constitute a coherent model of the parallel optical interconnect, a model that can be evaluated with a circuit simulator. I will mention how this analog modelling could be used for optimisation of the interconnect itself, and for simulation and timing verification within a digital system. For this timing verification part, just modelling the typical behaviour of the optical links doesn't suffice, you additionally need to take random effects into account , for instance to obtain jitter and skew figures. Here I will enumerate the most important stochastic effects in POI. To conclude, I will show you our measurement setup for one important noise effect, the impact of electrically coupled noise through the CMOS substrate on the bit error rate of optical links. EDA modelling of POI with direct CMOS-optics hybridization

Application: optimization of the POI Choices for operating currents, analog circuit design, numerical aperture, physical dimensions… Improvement at one place can get lost elsewhere Increase of numerical aperture of fiber better coupling less bending losses worse coupling (not to scale) Choices  parameter extraction  simulation  performance  examine the opposite direction EDA modelling of POI with direct CMOS-optics hybridization

CMOS substrate noise Simultaneous switching noise can disturb receiver circuits (figure: Cadence) EDA modelling of POI with direct CMOS-optics hybridization

Substrate noise measurement setup EDA modelling of POI with direct CMOS-optics hybridization