System-on-Chip Design Data Flow hardware Implementation Hao Zheng Comp Sci & Eng U of South Florida 1.

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Presentation transcript:

System-on-Chip Design Data Flow hardware Implementation Hao Zheng Comp Sci & Eng U of South Florida 1

Single-Rate SDF to Hardware Single-rate SDF: all production/consumption rates are a fixed number = 1. – The entire circuit controlled by a single clock. Implementation – Actors -> combination circuits – Queues -> wires – Initial tokens -> registers. 2

Single-Rate SDF to Hardware 3

4 Can lead to long combination paths.

Pipelining: Break Long Comb. Paths 5

6

7

8

Pipelining: Pitfall 9 Do Not add initial tokens unless they can be injected by a sequence of actor firings.

Multi-Rate Expansion (Sec ) 10 This single-rate DFG can be mapped to HW as shown previously.

HW/SW Hybrid Implementation 11 Interface btw. HW & CPU Interface btw. SW & CPU

Reading Guide Section , the CoDesign book. 12