WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Work Package 2 Radiation-hard ASIC building blocks for detector data readout José Pedro Cardoso

Personal Data Name: José Pedro Cardoso Nationality: Portuguese Age: 36 Education : MSc. in Electrical and Computer Engineering BSc. In Electronics and Telecommunications Engineering Joined ACEOLE’s Program: 1 st of June /07/20102

Accelerator Concepts Training and Education Project Timeline References 06/07/20103

The LHC 06/07/20104 Source:[1]

Accelerator Concepts Project Training and Education Timeline References 06/07/20105

Education - PhD in Electrical and Computer Engineering Title: Design of Low-Noise and Radiation Tolerant Readout Systems 1 st semester (2009/2010) Microelectronic and Micro-electro-Mechanical Technologies Test and Design for Testability Digital Communication Systems Seminars Projects: Design of a low-phase noise VCXO running at 80 MHz Design of a jitter measurement circuit, based on a new Vernier Delay Line Mem’s Based Oscillator 06/07/20106

Training On- job Training Phase Locked Loops Noise theory Cadence and MatLab Courses 2 day course – “Leaders in Science” Team work Self-Confidence Establish better personal and work connections between ACEOLEs. 06/07/20107

Accelerator Concepts Project Training and Education Timeline References 06/07/20108

Proposed Solution Circuit is divided as follows: PLL, BIST, Control and Fuse Banks. PLL is capable of Lock Detection and Automatic Oscillation Amplitude Control Built-in Self Test is capable of: Calibration (on-line and off-line) Frequency Offset Measurement Jitter Measurement Control block is able of controlling every action on the circuit and interact with the user Fuse bank acts as a PROM/RAM 06/07/20109

Phase Locked Loop Phase Locked Loop (PLL) Measures the difference input phase of two signals Based on, mainly, in the following blocks: Phase Detector, Loop Filter, Voltage-Controlled Oscillator Frequency Divider – N-Integer PLL with a dividing factor of 2 06/07/ Stand-alone operation The circuit should be low noise and insensitive to Process-Voltage- Temperature (PVT). A voltage is applied to the VCXO in order to generate the central frequency The output frequency will be 80 MHZ

Jitter Measurement Circuit Vernier Delay Line: is based on the delay line method. Time resolution is determined by a logic buffer delay. Two delay buffer chains are used: buffer’s delay in the upper chain is slightly higher than buffer’s delay in the lower delay chain, thus sub-gate timings can be achieved. Drawbacks: VDL has N stages and 2N delays, it makes this structure quite dependent on the technology used, resolution one gate delay and is area inefficient. Source:[2] 06/07/ Source:[2]

Jitter Measurement Circuit Modified Vernier Delay Line features: one counter instead of N counters in order to get the CDF, the simulation must be done N times. Advantages: Avoids a large waist of silicon area since only one counter is used. Disadvantages fabrication’s process dependent, because gate delays are PVT sensitive. Large measurement uncertainty Solution Replace all the delays by a single delay in each path, the circuit will be almost independent of the technology. Source:[2] 06/07/201012

Jitter Measurement Circuit Component-Invariant VDL [2] Uses inverters to cause the delay between data and clock, and then its output is fed back to the input. The oscillators will run with a period of 2 τ s or 2 τ f. Each inverter will delay the leading edge of the data signal in respect to clock signal by an amount of 2 Δτ seconds. To measure accurately timing the circuit should be able to detect rising edges of data/clock. Source:[2] 06/07/201013

Other Blocks (not developed yet) Calibration PLL mode - the auto calibration feature allows centring of the VCXO tuning range relating to the reference clock frequency. Oscillator mode - the auto calibration logic can be used to quickly choose the VCXO parameters that have to be programmed in the Fuse-Bank to tune the oscillation frequency. Frequency Offset Measurement Measures the offset between the central frequency and a reference Fuse Bank Fuses the default configuration of the PLL, after calibration. Uses a dynamic memory to operate in modes demanded by the user Control Interface Controls all the circuit operation and interfaces with the user with a 8-bit bus. AOAC The amount of power must be chosen according to decrease phase-noise, and not excite other resonant modes of the crystal, rather than the sheering of the crystal. 06/07/201014

Accelerator Concepts Training and Education Timeline Project References 06/07/201015

Timeline May January 2011 Design of a Phase Locked Loop with Built-In and Self test capabilities. The design should focus on a very low phase-noise circuit. Tape-out of the circuit Feb Mar 2011 Design and setup of the test session (pcb design, tester software, radiation lab setup) Test of the circuit Apr July 2011 Doctoral Programme Second Semester. Write an article to target conferences Sep Jun 2012 Development of a 10 GHz VCO Attend to targeted conferences Jun Sep 2012 Dissertation’s writing. 06/07/201016

References [1] - [2] - Chan, A. & Roberts, G. (2002), 'A deep sub-micron timing measurement circuit using a single-stage Vernier delay line''Custom integrated circuits conference', /07/201017

Thank you for your attention 06/07/201018

Backup Slides 06/07/201019

Functional Diagram PLL Generate Reference Clock BIST Recover the Input Signal Test and calibrate the Circuit Adjust the circuit’s parameters 06/07/201020

The Problem 06/07/201021

Main Project GBTX The GBTX is a radiation tolerant chip that can be used to implement bidirectional multipurpose optical links for high-energy physics experiments. The target applications are: data readout, trigger, timing, fast/slow control and monitoring links [1]. 06/07/201022

PLL specifications Crystal frequency = MHz Locking range = MHz ± 8 kHz Output Jitter < 7 ps 130 nm CMOS Technology One frequency multiplication mode: × 2 Power voltage: 1.5 V 10 GHz VCO for High-Speed Transceiver Very low-phase noise characteristics 06/07/201023

Stand-Alone VCXO Stand-alone operation Only VXCO is working The circuit should low noise insensitive to Process-Voltage- Temperature (PVT). A voltage is applied to the VCXO in order to generate the central frequency The output frequency will be 80 MHZ 06/07/201024

Jitter Measurement Circuit After each flip-flop either data leads the clock signal or lags the clock signal. When the data lags the clock the flip-flop latches to a logic level ‘0’, thus counter will not count. Disadvantage: resolution depends on τ, and finally on technology. This circuit can only measure timing till a gate delay. Source:[2] 06/07/201025