ESilicon Confidential IP Strategy Discussion 1.0 November, 2000.

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Presentation transcript:

eSilicon Confidential IP Strategy Discussion 1.0 November, 2000

2 eSilicon Confidential Major Topics Associated with IPs Priorities Customer-driven? Market Dynamics Platforms? Bus Architecture? eSilicon Own IP Dev.? How many IP vendors can we support? General Purpose (CPU, Analog) vs. Appl. Specific (PHY, Serdes) eSilicon IP/Supplier Roadmap Business Suppliers’, Customers’, eSilicon’s POV Licensing Model Licensing T&C’s Licensing Fees & Royalties Re-distribution Right to Customers & Design Federation Partners Competitive Analysis Issue with eS Plan Technical & Support (Rakesh) Hard vs. Soft IP Validation & Audit Test Chip? IP Test Strategy Standard Compliance – VSIA? Deliverable from Suppliers Repository & Revision Control Support & Training Model Infrastructure & Resources Spec. Review w/ Customers IP Partner Selection Process/Criteria Contractual & Legal Who is responsible if the design (IP) does not work? What do we guarantee to customers? eSilicon Strategies

3 eSilicon Confidential Market Strategy Phase II: eS Design is our ASIC engagement strategy. Focus on mid-complexity & performance segments of: Peripheral, Consumer, Wireline & Wireless Peripheral: Storage Area Network (SAN), Network Attached Storage (NAS), Consumer Storage Consumer: Digital TV, DVD, Set Top Box Wireline: xDSL, Voice over IP/DSL Wireless: Internet Data Access (Handset), PDA Phase IV: Add Platforms to eS Design to move us into an SoC/ASSP strategy. Focus on communications system knowledge…this is where high margin (and valuation) will be. What will make our offering stronger - Accessibility of silicon-proven applications specific IP cores, including high-speed or custom I/Os.

4 eSilicon Confidential Priorities Customer-driven? It’s the rule. If we rely too much on specific customers’ priorities, it’s going to be chaotic & we may not be able to respond to the req’s fast enough. Market Dynamics IP & Reuse are shifting toward applications specific. We need to assess the IP req’s for the targeted applications – SAN, NAS, Consumer Storage, DVT, DVD, STB, xDSL, VoIP/DSL, 3G Handset, PDA. Platforms? Bus Architecture? The TAB did not rank platform as a high priority. OEMs are defining their ASIC architecture for product differentiation. Platform is an ASSP strategy. eSilicon Own IP Dev.? Yes. Focus on custom I/Os, analog functions, & applications specific IPs that are commercially not available, such as 2.5G Serdes. If we do develop our own IPs, how do we fund the activities? The most logical choice is through the production margin. We should develop a ROI model whenever internal IP development is requested. How many vendors can we support? IP access is one of the top req’s to compete in the market place. We have to support whatever necessary from design POV. We do need a decision making process for vendor selection.

5 eSilicon Confidential Priorities (cont…) Standard Cell Libraries, High Standard I/Os, High PLL, OSC, High SRAM/ROM/FIFO, High CPU,High DSP (Handset)Medium High DAC/ADC (Consumer), Medium High Serdes (Network),Medium High Interfaces – PCI/USB/1394,Medium High High Speed I/OMedium DRAM/CAM/NVM, Medium DRAC,Medium Programmable Core,Low Medium Firmware.Low Medium * Need to assess the IP availability commercially.

6 eSilicon Confidential Deliverable from Suppliers Datasheet. Specifications. IP Usage White Papers. (Applications Specific) C Model or HDL Simulation Model. Testbench. RTL Codes, Synthesis Scripts, & Timing Constraints. (soft) Timing Model /.lib (hard) Gate Level V’LOG Model w/ Delay Calculator & SDF Support. (hard) DFT Strategy. LEF & GDSII (hard)