CEC 220 Digital Circuit Design Introduction to VHDL Friday, February 21 CEC 220 Digital Circuit Design Slide 1 of 10

Lecture Outline Friday, February 21 CEC 220 Digital Circuit Design Introduction to VHDL Slide 2 of 10

Introduction to VHDL Friday, February 21 CEC 220 Digital Circuit Design Slide 3 of 10 Large digital systems are unwieldy to design manually  E.g. design a H.264 video transcoder Hardware Description Languages (HDL) allow for design automation  Design  Simulation  Synthesis  Verification RTL: Register Transfer Level ESL: Electronic Sys Level

Introduction to VHDL VHDL Description of Combinational Logic Circuits Friday, February 21 CEC 220 Digital Circuit Design Slide 4 of 10 Basic example E <= D or (A and B); Signal_Name <= Expression; Behavioral Description

Introduction to VHDL VHDL Description of Combinational Logic Circuits Friday, February 21 CEC 220 Digital Circuit Design Slide 5 of 10 Basic example Assignment operator Concurrent statements Evaluated anytime variables changes If a delay time is not specified then the default is used Dataflow Description

Introduction to VHDL VHDL Description of Combinational Logic Circuits Friday, February 21 CEC 220 Digital Circuit Design Slide 6 of 10 A Second Example: CLK <= not CLK after 10 ns; A concurrent statement

Introduction to VHDL VHDL Description of Combinational Logic Circuits Friday, February 21 CEC 220 Digital Circuit Design Slide 7 of 10 Consequences of a concurrent statement

Introduction to VHDL VHDL Description of Combinational Logic Circuits Friday, February 21 CEC 220 Digital Circuit Design Slide 8 of 10 VHDL Syntax:  Signal names and other VHDL identifiers may contain letters, numbers, and the underscore character (_).  An identifier must start with a letter, and it cannot end with an underscore. VHDL is mostly case insensitive.  Thus, C123 and ab_23 are legal identifiers, but 1ABC and ABC_ are not.  Every VHDL statement must be terminated with a semicolon. White space is ignored.  In VHDL double dash (--) precedes a comment.  Words such as and, or, and after are reserved words with special meanings.

Introduction to VHDL VHDL Description of Combinational Logic Circuits Friday, February 21 CEC 220 Digital Circuit Design Slide 9 of 10 VHDL Operators:  Binary Logical Operators: and, or, nand, nor, xor, xnor  Relational Operators: =, /=,, >=  Shift Operators: sll, srl, sla, sra, rol, ror  Arithmetic Operators: +, -, &, *, /, mod, rem concatenation

Introduction to VHDL VHDL Description of Combinational Logic Circuits Friday, February 21 CEC 220 Digital Circuit Design Slide 10 of 10 Vector Operations

Introduction to VHDL VHDL Description of Combinational Logic Circuits Friday, February 21 CEC 220 Digital Circuit Design Slide 11 of 10 VHDL Models for Multiplexers sel <= A & B; -- select signal with sel select F <= I0 when “00”, I1 when “01”, I2 when “10”, I3 when “11”; F <= I0 when (A = ‘0’) else I1; Conditional assignment Selective assignment

Introduction to VHDL VHDL Description of Combinational Logic Circuits Friday, February 21 CEC 220 Digital Circuit Design Slide 12 of 10 Examples:  Implement the following VHDL conditional statement using two 2:1 MUXs: o F <= A when D=‘1’ else (B when E = ‘1’ else C);  Given that A <= “01101” and B <= “11100”, what is the value of: o F<= (not B & ‘1’ or A & ‘1’) and ‘1’ & A;

Introduction to VHDL VHDL Description of Combinational Logic Circuits Friday, February 21 CEC 220 Digital Circuit Design Slide 13 of 10

Next Lecture Friday, February 21 CEC 220 Digital Circuit Design More VHDL  Entity, architecture, modules, arrays, … Slide 14 of 10