FGM peer CDR I/F - 1 Berlin, April 6, 2004 Digital Interface (I/F) Aris Valavanoglou Institut für Weltraumforschung (IWF) Austrian Academy of Sciences

FGM peer CDR I/F - 2 Berlin, April 6, 2004 Command & Data Interface Based on THEMIS IDPU backplane specification Serial protocol synchronized to a 2^23 Hz clock (CLK8MHz) FGE receives its own set of CDI signals CLK (continuous signal provided by DCB) –2^23 Hz (CLK8MHz) –1 Hz (CLK1Hz) Command (CMD) FGE returns messages via two telemetry (TLM) signals –TMH (128 Hz vector rate continuously) –TML (4 … 128 Hz per command)

FGM peer CDR I/F - 3 Berlin, April 6, 2004 Serial Interface Circuit Two clock signals –2^23 Hz (~8.4 MHz) –1 Hz One Command Line Two Telemetry Lines –High Rate (TMH) –128 vectors/sec –Low Rate (TML) –Command able –4 vectors/sec –8 vectors/sec –16 vectors/sec –32 vectors/sec –64 vectors/sec –128 vectors/sec x2: CLK1Hz and CLK8MHz x2: TMH and TML

FGM peer CDR I/F - 4 Berlin, April 6, 2004 Synchronization by first non-zero (Start) bit after 25 zeros 24-bits long 8-bit identifier in the MSB (FGE CMD_ID = $8x) 16-bit data field in the LSB (CMD_DATA) Start, Stop and odd Parity bit (calculated without Start bit) Data transferred MSB first FGE clocks in the data bits on the falling edge of CLK8MHz Wrong commands rejected and reported to IDPU via TLMH Command Interface (F5) Command I/F Timing

FGM peer CDR I/F - 5 Berlin, April 6, 2004 Commands List of Commands: Page1/3 CMD_IDCommand# of Bits (I+C)Remark 0x81Control Word0+9Written to the control-register of FPGA SE/IF: Bit 0: 1/0Start / Stop Bit 1: 1/0Standard (default) / Calib. mode Bit 2: 1/0Excitation on / off Bit 3: 1/0Feedback Relais on (default) / off Bit 6-4:0004 Hz (TML data rate, default) Bit 6-4:0018 Hz (TML data rate) Bit 6-4:01016 Hz (TML data rate) Bit 6-4:01132 Hz (TML data rate) Bit 6-4:10064 Hz (TML data rate) Bit 6-4: Hz (TML data rate) Bit 8/7: 00Filter mode 1 Bit 8/7: 01Filter mode 2 (default) Bit 8/7:10Filter mode 3 Bit 15-9spare CommandCMD_ID [hex]Command Data Field [hex] C23-C20C19-C16C15-C12C11-C8C7-C4C3-C0 Start: Control word: Start / Stand. / Exc.on / Rel.on / 32Hz / FiltM B 1011 F 1111 Example:

FGM peer CDR I/F - 6 Berlin, April 6, 2004 Commands List of Commands: Page2/3 CMD_IDCommand# of Bits (I+C)Remark 0x82Phase0+16Phase 0x83Sampling0+8Number of sampling periods M in FPGA SE 0x84K1x0+16Field calculation in FPGA IF 0x85K1y0+16Field calculation in FPGA IF 0x86K1z0+16Field calculation in FPGA IF 0x87K2x0+16Field calculation in FPGA IF 0x88K2y0+16Field calculation in FPGA IF 0x89K2z0+16Field calculation in FPGA IF 0x8ADACx14+12Setting of DACx1 in calibration mode 0x8ADACy14+12Setting of DACy1 in calibration mode 0x8ADACz14+12Setting of DACz1 in calibration mode 0x8ADACx24+12Setting of DACx2 in calibration mode 0x8ADACy24+12Setting of DACy2 in calibration mode 0x8ADACz24+12Setting of DACz2 in calibration mode

FGM peer CDR I/F - 7 Berlin, April 6, 2004 Commands List of Commands: Page3/3 CMD_IDCommand# of Bits (I+C)Remark 0x8BOffset X2+14Offset for B calibration 0x8BOffset Y2+14Offset for B calibration 0x8BOffset Z2+14Offset for B calibration 0x8C--spare 0x8D--spare 0x8E--spare 0x8FReset0+0Reset

FGM peer CDR I/F - 8 Berlin, April 6, 2004 Same format for TMH and TML 16-bit long message word Plus Start bit Message preceded by 17 zeros End of message indicated by Zero instead of Start bit again FGE message consists of 3 x 24-bit vectors Each vector sign extended into 2 x 16 bit words FGE message length is 6 x 16 words (X-MSW, X-LSW, Y-MSW …) Telemetry Interface Telemetry I/F Timing

FGM peer CDR I/F - 9 Berlin, April 6, 2004 Telemetry Interface (F5) Extented TLMH Message with Status Information 32 bit message (2 x 16 bits) 24 bit FGM Data8 bit Status 24 bit FGM Datafree 24 bit FGM Datafree X-MSW (16 bits)X-LSW (16 bits) X - Vector Y - Vector Z - Vector

FGM peer CDR I/F - 10 Berlin, April 6, 2004 Telemetry Interface (F5) Status BitX-MSW BitStatus Bit High 08Command parity bit error 19Command stop bit error 210Calibration mode 311Feedback relais X open 412Feedback relais Y open 513Feedback relais Z open 614Filter mode LSB (bit 7 of control word) 715Filter mode MSB (bit 8 of control word) Status Bits

FGM peer CDR I/F - 11 Berlin, April 6, 2004 Synchronization Time Synchronization Constant delay between data acquisition and data transmission (derived from CLK8MHz) Time stamping done by IDPU Start of data acquisition with CLK1Hz (one second) sync Clock Timing

FGM peer CDR I/F - 12 Berlin, April 6, 2004 Propagation Delay (F6) Ch1: CLK EGSE output Ch2: CLK after Line Drivers Ch3: TLM after Line Drivers Ch4: TLM FGM output 1/2 23 = ns Measured with 74HCXXX Types and Actel ProASIC 500

FGM peer CDR I/F - 13 Berlin, April 6, 2004 Propagation Delay (F6) TypeVccTATA Min DelayMax Delay 54AC2405 V-55°C to +125°C 1.0 ns8.5 ns 54AC145 V-55°C to +125°C 1.0 ns12.0 ns RTSX-S Input 5 V-55°C to +125°C -1.1 ns RTSX-S Comb. Cell 5 V-55°C to +125°C -1.2 ns RTSX-S Output 5 V-55°C to +125°C -3.8 ns For one complete loop (DCB– FGM – DCB) worst case: 51.9 ns Maximum delay allowed (0.5/2 23 ): 59.6 ns 2x 54AC240 2x 54AC14 1x RTSX-S Input 1x RTSX-S Output 5x RTSX-S Comb. Cell