Peter LICHARD CERN (NA62)1 NA62 Straw tracker electronics Study of different readout schemes Readout electronics frontend backend Plans

Peter LICHARD CERN (NA62)2 NA62 straw tracker data flow 2 STRAW READOUT & CONTROL STRAW READOUT & CONTROL STRAW READOUT & CONTROL STRAW READOUT & CONTROL 1 chamber contains 2 modules 1 module contains 2 views 1 view is a smallest readout system 28 FE boards from 1 view (2 groups of 14 boards) 2 Straw Readout Boards 2 fibers TELL1 Serving 2 chambers (2x4 views)

NA62 straw tracker FrontEnd electronics First experience with frontend board connector already torn off and PCB damaged heavy cable, mechanical fixation not easy special thick PCB, vacuum tight, drilling not possible only SMD components, vertical (no space on the side) vertical SMD connectors usually considered board-to-board Peter LICHARD CERN (NA62)3

NA62 straw tracker FrontEnd electronics with VHDCI connector Front end connectivity Data to DAQ on 16 differential (LVDS) lines for group of 16 straws Control from DAQ on 5 differential lines (I2C, TP) Power 8V changing connectors for HONDA VHDCI, 68 pins Standard SCSI halogen- free cable Submit modifications to CERN design service this week Cable problem will stay Peter LICHARD CERN (NA62)4

NA62 straw tracker FrontEnd electronics Peter LICHARD CERN (NA62)5

NA62 straw tracker FrontEnd electronics with RJ45 connector Use smaller cable to circumvent mechanical problems Serial I/O interfaces FPGA contains TDC, derandomizer, serial link Using high speed serial links can also help with crosstalk as CARIOCA has a bandwidth of ~20 MHz Data flow from 1 FE board –30 bits BX + 3(4) bits fine time + r/f edge + 4 bits straw ID + 1 bit control = 40 bits –8B10B coding –~800 MBits/s possible in CYCLONEIII, aim for ~160 MBits/s –Category 5e ethernet cable (shielded), 5 meters –Average rate 33kHz Need 42 MBits/s 1 link 160 Mbits/s sufficient –Max rate 500kHz on some straws Need 320 Mbits/s 2 links 160 MBits/s (using spare output), can also increase the speed if needed –Derandomizer on TDC chip to prevent data loss

NA62 straw tracker FrontEnd electronics with RJ45 connector Control flow from FE board to backend –Using the same line as for data, used only in SPS gaps –Read back threshold values –Read back FPGA registers Control input –Uses 1 line, Manchester coding, 80MHz ? –FPGA control –Writing thresholds –Sending even/odd TP –Sending BC counter reset Clock –Uses 1 line –Could use control line for clock as well, but better separate line for lower jitter Spare line –Used for data transmission for highest rate straws

NA62 straw tracker FrontEnd electronics with RJ45 connector Front end connectivity ethernet connector (RJ45) 4 differential lines Data to DAQ on 1 differential (LVDS) line for group of 16 straws Control from DAQ on 1 differential line precise clock 40 MHz 1 differential line spare (output for high rate straws?) Power 8V and DCS on separate connector Use standard halogen free ethernet cable Submit modifications to CERN design service next week Peter LICHARD CERN (NA62)8 TDC and serializer CYCLONEIII FPGA in 256 pins FBGA package SMD RJ45 Vertical connector

NA62 straw tracker electronics Required TDC resolution –‘fast’ gas Ar/CO2, muon test beam –On X is bin (not resolution) –Blue, unknown R-T dependence –Red, known R-T dependence

Peter LICHARD CERN (NA62)10 NA62 straw tracker electronics plans Frontend –Equip new detector prototype with prototype FE boards based on CARIOCA and equipped with VHDCI TDC+ethernet connectors –Lab measurements CARIOCA alone connected to the prototype Signal shape (afterpulses) crosstalk, different straw terminations Noise etc 10

Peter LICHARD CERN (NA62)11 NA62 straw tracker electronics plans Backend –testbeam Build small VME readout, possibly scalable and upgradable to full DAQ –VME 9U board –8 connectors (groups of 16 straws), 68 pins VHDCI connector »4 served by FPGA TDC with 1.5ns or 3.1ns bin »4 served by HPTDC –4 ethernet connectors, 8 pins RJ45 »TDC is on the frontend »Only low level event building –Preliminary study shows TDC with ~1ns resolution (1.5ns bin) feasible for 16 straws in ALTERA CYCLONE III FPGA (~20 Euro) »~2 ns resolution (3ns bin) ?, using slower chip (~12 Euro) –Data collected by SBC through VME –Used for lab tests and testbeam

Peter LICHARD CERN (NA62)12 NA62 straw tracker electronics plans Backend –Final If serial link solution works –number of SRBs reduces to 4/chamber –All readout fits to 1 crate VME 9U Need to find housing for 2 TELL1 boards and define connection (fiber/Cu) –TELL1 needs non-standard VME crate, impossible to plug in crate with Straw Readout Boards 12