ADAPTIVE CACHE-LINE SIZE MANAGEMENT ON 3D INTEGRATED MICROPROCESSORS Takatsugu Ono, Koji Inoue and Kazuaki Murakami Kyushu University, Japan ISOCC 2009

Outline  Introduction  Software Controllable-Variable Line Size (SC-VLS) Cache  Evaluation  Summary 2

3D Integration  Stacking the main memory on processors  Connecting them by wide on-chip buses  The memory bandwidth can be improved 3

Motivation 4  3D stacking makes it possible to reduce the cache miss penalty  We can employ larger cache line size in order to expect the effect of prefetching  But… if programs don’t have high spatial localities of memory references  It might worsen the performance  A large amount of energy is required!

Software-Controllable Variable Line-Size Cache (1/3) 5  We propose SC-VLS cache  It attempts to optimize the amount of data to be transferred between cache memory and main memory  When a program does not require high memory bandwidth ⇒ SC-VLS cache reduces the cache line size

Software-Controllable Variable Line-Size Cache (2/3) 6  Features  SC-VLS cache doesn’t require any hardware monitor to decide the line size  Advantages  SC-VLS cache reduces energy consumption with trivial hardware overhead

Software-Controllable Variable Line-Size Cache (3/3) 7  Adequate line size analysis  Before an application program is executed, we analyze an adequate line size of each function  Code generation  Line size change instructions are inserted into start of functions in original program code  The instruction sets status register to indicate an adequate line size

Adequate Line Size Analysis - Example- 8

Evaluation  Simulator  SimpleScalar and CACTI  Benchmark programs  10 programs (MiBench)  Input data sets  Analysis phase: small  Execution phase: large  The SC-VLS cache can dynamically choose four line sizes;  32B, 64B, 128B and 256B 9

Energy

Performance 11

Summary  3D integration  can improve memory bandwidth  makes it possible to reduce the cache miss penalty  SC-VLS cache  can dynamically change the line sizes  reduces the energy consumption up to 75% 12

THANK YOU ACKNOWLEDGEMENT This research was supported in part by New Energy and Industrial Technology Development Organization

Architecture 14

Adequate Line Size Analysis 15  We execute cache simulation with each line size independently to determine an adequate line size 1. An average cache miss rate of each function is calculated 2. We compare the average cache miss rates with all line size candidates 3. A line size which the cache miss rate is the smallest is determined as an adequate line size

Energy Model 16 # L1 memory access Total energy of stacked DRAM average energy for a cache access Total energy of $L1 # main memory access average energy for a cache access # activated DRAM sub-array

Average SC-VLS Cache Line Size BenchmarksAverage SC-VLS cache line size (B) bitcount81.94 mad tiff2bw dijkstra rijndael_enc64.82 rijndael_dec33.01 sha adpcm_enc adpcm_dec lame