The Intel486 Processor Basic Bus Cycle D.Geneus 11/23/1996.

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Presentation transcript:

The Intel486 Processor Basic Bus Cycle D.Geneus 11/23/1996

Topics Basic Operation of the 486 Processor Basic Microcomputer System with Input/Output(I/O) Ports and Peripherals Physical Memory and IO space Basic 486 Processor Read Bus Cycle Basic 486 Processor Write Bus Cycle References

Basic Operation of the 486 Processor The Intel 486 Processor is a device that executes a program (list of instructions) by repeatedly cycling through the following basic steps: 1. Fetch the next instruction from memory 2. Read an operand if required by the instruction. An operand is a quantity to be operated on as directed by its asscotiated instruction. 3. Execute the instruction (do what the instruction says) 4. Write the result back into memory ( if required by the instruction)

Basic Microcomputer System with Input/Output(I/O) Ports and Peripheral REAL TIME CLOCK PROG TIMER PROG INTERRUPT CONTROL DRAM BIOS EPROM FPGA 1. chip select generation 2. byte swap operation 3. state machines 4. ready signal 486 CPU DATA BUS CONTROL BUS ADDRESS BUS

Physical Memory and IO space NOT Accessible 64K byte H 0000FFFFH I/O Space Physical Memory 4G byte FFFFFFFFH H Physical Memory Space byte 1byte 2byte 3byte 4 32 Bit wide Organization highest addressed byte lowest addressed byte

Basic 486 Processor Read Bus Cycle valid address valid data read strobe ready TiT1T2T1T2 CLOCK 33 MHz ADSN ADDRESS WRITE/READ DATA READY

Basic 486 Processor Write Bus Cycle valid address valid data write strobe ready TiT1T2T1T2 CLOCK 33 MHz ADSN WRITE/READ DATA READY ADDRESS

Digital Fundementals, fourth edition, Floyd Intel Military Products data book Local Representative: Zues Electronics 25 Uptown drive Wilmington, Ma Tel: or Fax: References