Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Bulk crystal growth melting points –silicon: 1420˚ C –GaAs: 1238˚ C –quartz: 1732˚ C starting material: metallurgical-grade silicon –by mixing with carbon, SiO 2 reduced in arc furnace T > 1780˚C: SiC + SiO 2  Si + SiO + CO –common impurities Al: 1600 ppm (1 ppm = 5 x cm -3 ) B: 40 ppm Fe: 2000 ppm P: 30 ppm –used mostly as an additive in steel

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Preparation of electronic-grade silicon gas phase purification used to produce high purity silicon – ~ 600˚C –crud + Si + HCl  SiCl 4 (silicon tetrachloride) SiCl 3 H (trichlorosilane) SiCl 2 H 2 (dichlorosilane) chlorides of impurities –trichlorosilane (liquid at rm temp), further purification via fractional distillation now reverse reaction –2SiHCl 3 + 2H 2 (heat)  2Si + 6HCl –after purification get Al: below detection B: < 1 ppb (1 ppb = 5 x cm -3 ) Fe: 4 ppm P: < 2 ppb Sb: 1 ppb Au: 0.1 ppb

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Czochralski crystal growth silicon expands upon freezing (just like water) –if solidify in a container will induce large stress CZ growth is “container-less” images from Mitsubishi Materials Silicon silhist0-e.html

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Diameter control during CZ growth critical factor is heat flow from liquid to solid –interface between liquid and solid is an isotherm temperature fluctuations cause problems! –already grown crystal is the heat sink balance latent heat of fusion, solidification rate, pull rate, diameter, temperature gradient, heat flow diameter inversely proportional to pull rate (typically ~ mm/min) images from Mitsubishi Materials Silicon pull direction seed rotation

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin increment solidified Diameter control during CZ growth critical factor is heat flow from liquid to solid –heat flux (power) balance heat released as solidifies thermal diffusion in liquid from hot liquid towards solidification interface thermal diffusion in solid from solidification interface towards cooler sides/end of boule += solid liquid dx = v pull dt ; dm =  A dx temperature latent heat of fusion –heat flux (power) released is –interface between liquid and solid should be an isotherm temperature fluctuations cause problems!

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Diameter control during CZ growth heat flow balance becomes solid liquid temperature increment solidified –so critical factor is relation between temperature gradient in boule and boule size thermal current proportional to cross sectional area A and v pull if the only heat sink were at the end of the boule: thermal resistance inversely proportional to A, directly proportional to length of boule l temperature change (“voltage”) = I thermal R thermal –or net effect: just what we got above! dT/dx independent of diameter  diameter doesn’t appear!!! 

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Diameter control during CZ growth solid liquid temperature increment solidified but most of the heat is lost via radiation from the SIDES of the boule! –thermal current still proportional to cross sectional area A  (diameter) 2 and v pull –if the heat sink is from sides of boule: thermal resistance inversely proportional to perimeter  diameter, temperature change (“voltage”) = I thermal R thermal  net effect: diameter is inversely proportional to pull rate

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Impurities in Czochralski Grown Silicon choice of crucible material is crucial: –must be stable at high temperatures (~1500˚ C) –carbon: saturates solution and causes poly growth –refractories: too much metal in materials –quartz: in exclusive use for silicon growth dissolution of quartz crucibles into melt is major concern: –function of relative velocity between melt & crucible –almost all oxygen present in silicon melt is due to the dissolution of the SiO 2 crucible –most of this oxygen evaporates in the form of SiO

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin when a volume of liquid freezes, if k < 1, what is concentration in solid? must be less than in liquid what happens to extra impurities? rejected into melt  increased [impurity] in melt if C o is initial melt concentration, and X is fraction solidified Doping and segregation effects during crystal growth when two dissimilar materials / phases are in contact, the concentration of an impurity across the interface is NOT NECESSARILY CONTINUOUS –segregation (distribution) coefficient 0 1

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Doping and segregation effects during crystal growth images from Mitsubishi Materials Silicon segregation effects can be used intentionally to purify semiconductor material –zone refining consists of repeated passes through the solid by a liquid zone 0 1 –float zone silicon used for high resistivity

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Oxygen in CZ Silicon concentrations typically in cm -3 range –segregation coefficient k ~ 1.25 more in solid than liquid –contact area between crucible and melt decreases as growth procedes –oxygen content decreases from seed to tang end effects of oxygen in silicon –~ 95% interstitial; increases yield strength of silicon via "solution hardening" effect –as-grown crystal is usually supersaturated (occurs above about 6 x )

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Oxygen complexes in silicon usually donor-like two classes of complexes: –"old thermal donors" very small silicon-oxygen atom clusters very rapid formation rates in ˚ C range (≥ /cm 3 sec) –"new thermal donors" slow formation rate above 500˚ C slow dissolution rate at high temperature –~10 13 cm 2 hours, 900˚ C –~10 11 cm 2 hours, 1150˚ C donor behavior possibly due to surface states of large SiO x complexes

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Gettering in Silicon Wafers devices fabricated only in the top five or ten microns of the wafer: use gettering to provide a sink for unwanted defects in the bulk of the wafer –gettering sites provide sinks for impurities generated during the processing “bulk” wafer “device” region back side damage bulk faults mobile impurities backside damage: (pre-gettering) –mechanical damage produces high strain regions –impurities nucleate on dislocations; if wafer stresses are kept small during subsequent processing dislocations will remain localized on back

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Intrinsic Gettering and Oxygen Precipitates wafer starting material: –initial oxygen content between ~3.5 and ~8 x cm -3 denuded zone formation: –high temperature step (1050˚ C) reduces interstitial oxygen content via diffusion of O to surface –formation of internal gettering sites: low temp step ( ˚ C) creates large reserve of small, stable oxygen precipitates higher temperature step ( ˚ C) causes growth of larger SiO x complexes subsequent thermal processing creates dislocation loops associated with SiO x complexes –actual starting material oxygen concentration and process determined by trial device fab and performance evaluation.

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Denuded zone preferential (decorating) etch used to reveal stacking faults and precipitates –OSF: oxidation induced stacking faults from: Sze, VLSI Technology, 2nd edition, p. 46.

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Wafer preparation boule forming, orientation measurement –old standard: “flat”perpendicular to direction; –on large diameter “notch” used instead images from Mitsubishi Materials Silicon inner diameter wafer saw wafer slicing – typically within ± 0.5˚ –, 2˚ - 5˚ off axis

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Wafer prep (cont.) lapping –grind both sides, flatness ~2-3  m ~20  m per side removed edge profiling etching –chemical etch to remove surface damaged layer ~20  m per side removed polishing –chemi-mechanical polish, SiO 2 / NaOH slurry ~25  m per polished side removed –gives wafers a “mirror” finish cleaning and inspection

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Wafer specifications –warp: distance between highest and lowest points relative to reference plane –bow: concave or convex deformation

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Wafer diameter trends desire is to keep number of chips (die) per wafer high, even as die size increases challenge: thermal nonuniformities, convection currents become more significant as diameter grows

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Wafer specifications –“next” generation: 300 mm wafer diameter –25x25 mm die size yields 89 complete die Sematech From Sematech document: International 300 mm Initiative, Technology Transfer # A-ENG

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Silicon wafer production 1999: billion square inches, $5.883 billion –$1.38 per square inch, $0.21 per square cm –100mm, 150mm: billion square inches (65.9% of total) –200mm: billion square inches (33.8%) –300mm: billion square inches of silicon (0.3%) 2000, expected: billion square inches, $6.475 billion 2001, expected: billion square inches 2003, expected: –200mm: billion square inches –300mm: billion square inches from EE Times, “Advanced silicon substrates prices rise as wafer glut eases” by J.Robert Lineback Semiconductor Business News (01/12/00, 2:04 p.m. EST)Semiconductor Business News

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Volume Silicon processing costs 2001 processing cost date –reference: ICKnowledge, advanced CMOS process, ~0.13 micron, 300mm wafers, ~25 mask levels: –about $5 per cm 2 –reference: ICKnowledge, –model assumes a 30, mm wafer per month fab running at 90% of capacity that’s about 21 million cm 2 / month! about 40 wafer starts per hour –2001 world-wide wafer starts, 8” (200mm) equivalent: ~5 million wafers per month (~1.5billion sq. cm per month) from MOSIS (ref –1.5 micron cmos ~$200 per square mm, 5 to 20 parts per lot  cost ~$4K- $1K per cm 2 –0.18 micron ~$1-2K per square mm for 40 parts  cost > ~$2.5K per cm 2

Dean P. Neikirk © 1999, last update February 13, Dept. of ECE, Univ. of Texas at Austin Silicon Oxides: SiO 2 Uses: –diffusion masks –surface passivation –gate insulator (MOSFET) –isolation, insulation Formation: –grown / “native” thermal: “highest” quality anodization –deposited: C V D, evaporate, sputter vitreous silica: material is a GLASS under “normal” circumstances –can also find “crystal quartz” in nature m.p. 1732˚ C; glass is “unstable” below 1710˚ C –BUT devitrification rate (i.e. crystallization) below 1000˚ C negligible