Solid-State Devices & Circuits

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Presentation transcript:

Solid-State Devices & Circuits ECE 442 Solid-State Devices & Circuits 4. CMOS Logic Circuits Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu

Digital Logic - Generalization De Morgan’s Law Distributive Law General Procedure Design PDN to satisfy logic function Construct PUN to be complementary of PDN in every way Optimize using distributive rule

CMOS Logic Gate Circuits Two Networks Pull-down network (PDN) with NMOS Pull-up network (PUN) with PMOS PUN conducts when inputs are low and consists of PMOS transistors PDN consists of NMOS transistors and is active when inputs are high PDN and PUN utilize devices In parallel to form OR functions In series to form AND functions

Pull-Down Networks

Pull-Up Networks

Basic Logic Function Basic Function INVERTER NOR NAND Symbol # Devices PUN 1 PMOS 2 PMOS-Series 2 PMOS-Parallel 2 NMOS-Parallel 2 NMOS-Series 1 NMOS # Devices PDN Truth Table

Pull-Down and Pull-Up Functions Pull-up network (PUN) Pull-down network (PDN) Key features When PDN switch is on, PUN switch is off and vice versa Conditions for being on and off are complementary

Pull-Down and Pull-Up PDN-parallel NMOS PUN-series PMOS Truth Tables

Pull-Down and Pull-Up PDN-Parallel and PUN-series are complementary When YDP in PDN-parallel is low, this means that either A or B (or both) is high. When either A or B (or both) is high, either transistor (or both) in PUN-series are offYUS=low When YDP in PDN-parallel is high, both A and B are low. Both transistors in PUN-Series are on creating a path to VDD. YUS=highYUS=YDP. PDN-Parallel and PUN-series are complementary

Pull-Down and Pull-Up PDN-Series NMOS PUN-Parallel PMOS Truth Tables

Pull-Down and Pull-Up PDN-Series and PUN-Parallel are complementary If YDS is low, both A and B must be high in which case both transistors in PUN-Parallel are off providing no path to VDDYUP=lowYUP=YDS. If YDS is high, then either A or B (or both) are off (low) in which case either QPA or QPB in PUN-Parallel will be on and present a path to VDD; thus YUP=high  YUP=YDS PDN-Series and PUN-Parallel are complementary

Two-Input NOR Gate

Two-Input NOR Gate Ideal Actual

Two-Input NAND Gate

Example Using De Morgan’s Law Pull-down network Pull-up network

Example 1 Evaluate Logic Function from pull down from pull up

Example 2 Implement the function pull up pull down

Exclusive-OR (XOR) Function pull up pull down