Demonstrations of RDBE-PFB Data Flow. Review the original PFB Data Flow.

Slides:

Advertisements

Similar presentations

1 Integration Testing CS 4311 I. Burnstein. Practical Software Testing, Springer-Verlag, 2003.

Advertisements

Lab7: Introduction to Arduino

© 2007 Cisco Systems, Inc. All rights reserved.Cisco Public 1 Version 4.1 Troubleshooting Working at a Small-to-Medium Business or ISP – Chapter 9.

Using an FPGA to Control the Protection of National Security and Sailor Lives at Sea Brenda G. Martinez, Undergraduate Student K.L. Butler-Purry, Ph.D.,

MotoHawk Training Model-Based Design of Embedded Systems.

© 2008 Cisco Systems, Inc. All rights reserved.CIPT1 v6.0—5-1 Implementing Media Resources, Features, and Applications Implementing Cisco Unified Video.

Unit 231 Software Engineering Introduction to SWE What is SDLC Phases of SDLC.

1 Performed By: Khaskin Luba Einhorn Raziel Einhorn Raziel Instructor: Rivkin Ina Spring 2004 Spring 2004 Virtex II-Pro Dynamical Test Application Part.

Characterization Presentation Spring 2006 Implementation of generic interface To electronic components via USB2 Connection Supervisor Daniel Alkalay System.

Illinois Institute of Technology

EE694v-Verification-Lect5-1- Lecture 5 - Verification Tools Automation improves the efficiency and reliability of the verification process Some tools,

WANs and Routers Routers. Router Description Specialized computer Like a general purpose PC, a router has:  CPU  Memory  System Bus Connecting Internal.

Introduction to Software Testing

Software Testing & Strategies

The 6713 DSP Starter Kit (DSK) is a low-cost platform which lets customers evaluate and develop applications for the Texas Instruments C67X DSP family.

© 2006 Cisco Systems, Inc. All rights reserved.Cisco PublicITE I Chapter 6 1 Characterizing the Existing Network Designing and Supporting Computer Networks.

Commercial Database Applications Testing. Test Plan Testing Strategy Testing Planning Testing Design (covered in other modules) Unit Testing (covered.

Infrastructure design & implementation of MIPS processors for students lab based on Bluespec HDL Students: Danny Hofshi, Shai Shachrur Supervisor: Mony.

DOS  In the 1980s or early 1990s, the operating system that shipped with most PCs was a version of the Disk Operating System (DOS) created by Microsoft:

DLS Digital Controller Tony Dobbing Head of Power Supplies Group.

VLBA Software Group Meeting RBDE Control via VSI-S Interface Miguel Guerra National Radio Astronomy Observatory (Socorro, NM) 2010 January 12.

Large Scale Software Systems Derived from Dr. Fawcett’s Notes Phil Pratt-Szeliga Fall 2010.

1 Programming of FPGA in LiCAS ADC for Continuous Data Readout Week 3 Report Jack Hickish.

BE-SECBS FISA 2003 November 13th 2003 page 1 DSR/SAMS/BASP IRSN BE SECBS – IRSN assessment Context application of IRSN methodology to the reference case.

Pre-OTS Testing in Penticton Sonja Vrcic Socorro, December 11, 2007.

Electrocardiogram (ECG) application operation – Part B Performed By: Ran Geler Mor Levy Instructor:Moshe Porian Project Duration: 2 Semesters Spring 2012.

Author Wayne M. Koski EVLA Monitor & Control Hardware PDR March 13, EVLA Monitor and Control Module Interface Board (MIB) Design.

Computer Architecture Lecture 2 System Buses. Program Concept Hardwired systems are inflexible General purpose hardware can do different tasks, given.

EEE440 Computer Architecture

Working with Xilinx Spartan 3 Embedded Systems Lab 2009.

Electrocardiogram (ECG) application operation – Part A Performed By: Ran Geler Mor Levy Instructor:Moshe Porian Project Duration: 2 Semesters Spring 2012.

Final Presentation Final Presentation OFDM implementation and performance test Performed by: Tomer Ben Oz Ariel Shleifer Guided by: Mony Orbach Duration:

Final Presentation Implementation of DSP Algorithm on SoC Student : Einat Tevel Supervisor : Isaschar Walter Accompanying engineer : Emilia Burlak The.

CASE (Computer-Aided Software Engineering) Tools Software that is used to support software process activities. Provides software process support by:- –

VLBA Implementation of the ROACH Digital Backend Jonathan Romney on behalf of the VLBA Upgrade development team NRAO / Socorro First International VLBI.

Proposal for an Open Source Flash Failure Analysis Platform (FLAP) By Michael Tomer, Cory Shirts, SzeHsiang Harper, Jake Johns

Version 10.1 Xilinx Tools Update Terry Filiba CASPER Workshop II.

1 Software Testing Strategies: Approaches, Issues, Testing Tools.

Test Plan: Introduction o Primary focus: developer testing –Implementation phase –Release testing –Maintenance and enhancement o Secondary focus: formal.

Reconfigurable Communication Interface Between FASTER and RTSim Dec0907.

24 Feb 2009ITCN 1 Introduction to Computer Networking M Clements.

SIDE SCAN HARDWARE CONFIGURATION

October Test Beam DAQ. Framework sketch Only DAQs subprograms works during spills Each subprogram produces an output each spill Each dependant subprogram.

Sub- Nyquist Sampling System Hardware Implementation System Architecture Group – Shai & Yaron Data Transfer, System Integration and Debug Environment Part.

SIDE SCAN HARDWARE CONFIGURATION HYPACK Connection Block Diagram GPS, single beam and tide data go into HYPACK ® SURVEY. Sidescan (with optional.

SEPTEMBER 8, 2015 Computer Hardware 1-1. HARDWARE TERMS CPU — Central Processing Unit RAM — Random-Access Memory  “random-access” means the CPU can read.

TOW May 2011 DBBC2 G. Tuccari – INAF Istituto di Radioastronomia.

1 Chapter 1 Basic Structures Of Computers. Computer : Introduction A computer is an electronic machine,devised for performing calculations and controlling.

Scalable Readout System Data Acquisition using LabVIEW Riccardo de Asmundis INFN Napoli [Certified LabVIEW Developer]

1 © 2004, Cisco Systems, Inc. All rights reserved. CCNA 2 v3.1 Module 2 Introduction to Routers.

RBSP Radiation Belt Storm Probes RBSP Radiation Belt Storm Probes RBSP/EFW CDR /30-10/1 647 Ground Support Equipment Will Rachelson University of.

Configuring Network Devices

Data Acquisition, Diagnostics & Controls (DAQ)

EE694v - Verification - Lect 12

Software Testing Strategies for building test group

Programming and Debugging with the Dragon and JTAG

Test Boards Design for LTDB

Metrics Replication Presentation for Maryland Staff September 26, 2002

Implementing VHDL Modules onto Atlys Demo Board

Next steps – with notes from during the meeting 17 March 2016

Next steps - with notes from during the meeting 24 March 2016

Serial Data Hub (Proj Dec13-13).

Computer Science I CSC 135.

AT91RM9200 Boot strategies This training module describes the boot strategies on the AT91RM9200 including the internal Boot ROM and the U-Boot program.

Introduction to Software Testing

QGen and TQL-1 Qualification

Chapter 8: Monitoring the Network

Presentation transcript:

Demonstrations of RDBE-PFB Data Flow

Review the original PFB Data Flow

Design Methodology Build a BSP to support the Roach Hardware. Haystack supportable design. Design using commercially availability tool flow. Code base needs to be maintained for life cycle of instrument. Design at the HDL level for code portability to future hardware architecture changes and device changes. Modular design for regression testing and verification of modules, especially when adding features to the design, upgrading tools and hardware. SVN repository for RDBE designs. Documentation.

Demonstration/verification of RDBE-PFB Data Integrity U-boot/LinuxDevice Driver/RDBE Server Application. Processing of commands via console and LAN port. FPGA load from USB Stick, NTFS Server and Flash. System support modules tested/verified. Signal Processing Modules are independently verified in hardware. Mk5B (2bit) format for Geodesy has been tested/verified. Additional processing applications can be implemented.

Data Flow Test setup Build top level module with DUT. Use signal/noise source as input to ADC. Run various (numerous) test on DUT. Collect 10Ge data packets using WireShark on PC. Analyze/verify data using Matlab, not only integrity but also timing. Conduct real time impulse response of filters to ensure correct coefficient ordering.

Task that still need to be completed Need to add Julian clock, level control and timing module. Phase Cal., 1 pps comparison module. Implement command interpreter with error checking. Implement VSI command set with error checking. RDBE Monitor application (Human Interface). Xport Monitor Application (External Monitoring, power reset). Documentation. Incrementally build PFB top level design (basically connect the SP modules together and test/verify at each stage). Testing with Mk5C when available. Operational testing. Comparison with iBOB. Implement 4Gbps version. NRAO DDC ?