Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 1 ECE 406 Design of Complex Digital Systems Lecture 11: Data Converter, LC-3 Instruction Set Spring W. Rhett Davis NC State University with significant material from Paul Franzon & Bill Allen

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 2 Summary of Last Lecture l How do you implement a state-machine when given a state-transition diagram? l Why in general do you need a reset-signal for a module? l What is the difference between synchronous and asynchronous reset signals?

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 3 Today’s Lecture l Data Converter Example continued l Review of the LC3 Instruction Set

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 4 Data Converter Specification l When a new 32-bit data word arrives at the input, the module stores it and then outputs the word as 4 bytes, starting with the MSB and ending with the LSB. l The arrival of a 32-bit word to be converted is signaled by a pulse on ready that is 3 clock cycles long. l The output of a byte of data is signaled by a one clock cycle pulse on new. The output byte is available during the new pulse and for one clock cycle after. Data Converter IN ready OUT new 32 / 8 /

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 5 Design Process l Step 1: Write Specification l Step 2: Draw Schematic » Ports » Registers » Datapath Logic » MUXes » Control Logic l Step 3: Write Verilog Code » Label Internal Signals » Map elements from schematic into code

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 6 Data Selector Schematic

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 7 Controller State Diagram

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 8 Data Converter (Style 1) module dataconv( input [31:0] IN, input clock, input ready, input reset, output reg [ 7:0] OUT, output reg new ); reg [31:0] value ; reg [ 3:0] state ;

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 9 Data Converter (Style 1) clock) if (reset) state <= 0 ; else case (state) 0: if (ready) state <= 1 ; else state <= 0 ; ………………

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 10 Data Converter (Style 1) clock) if (state == 1) value <= IN ; or value) case (state) 2, 4, 6, 8: new <= 1 ; default: new <= 0 ; endcase

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 11 Data Converter (Style 1) or value) case (state) 0, 1, 2, 3: OUT <= value[31:24] ; 4, 5: OUT <= value[23:16] ; 6, 7: OUT <= value[15: 8] ; default: OUT <= value[ 7: 0] ;

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 12 Data Converter (Sophisticated Style) module dataconv(IN, clock, ready, reset, OUT, new); input clock,reset,ready; input [31:0] IN; output [7:0] OUT; output new; reg [7:0] OUT; reg new; reg [31:0] value; reg [3:0] state; clock) begin if (reset) state <= 0; else case(state) 0: begin if (ready) state <= 1; else state <= 0; new <= 0; end 1: begin state <= 2; value <= IN; end 2: begin state <= 3; OUT <= value[31:24]; new <= 1; end

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 13 Data Converter (Sophisticated Style) 3: begin state <= 4; new <= 0; end 4: begin state <= 5; OUT <= value[23:16]; new <= 1; end 5: begin state <= 6; new <= 0; end 6: begin state <= 7; OUT <= value[15:8]; new <= 1; end 7: begin state <= 8; new <= 0; end 8: begin state <= 9; OUT <= value[7:0]; new <= 1; end 9: begin state <= 0; new <= 0; end default: begin state <= 0; end endcase end endmodule

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 14 Data Converter (Style 3) module dataconv( input [31:0] IN, input clock, input ready, input reset, output reg [ 7:0] OUT, output new ); // no reg reg [31:0] value ; reg inputRdy ; // ready for input reg ioAction ; // I/O occurs on next cycle reg [ 1:0] byteIndex ; // byte to output

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 15 Data Converter (Style 2) clock) if (reset) begin ioAction <= 0 ; inputRdy <= 1 ; byteIndex <= 0 ; end

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 16 Data Converter (Style 2) clock) …………………………… else if (inputRdy) begin ioAction <= !ioAction && ready ; inputRdy <= !ioAction ; byteIndex <= 0 ; end

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 17 Data Converter (Style 2) clock) …………………………… else begin ioAction <= !ioAction ; inputRdy <= ioAction && byteIndex==3 ; byteIndex <= ioAction ? byteIndex+1 : byteIndex ; end

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 18 Data Converter (Style 2) clock) if (inputRdy && ioAction) value <= IN ; assign new = ioAction && !inputRdy ;

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 19 Data Converter (Style 2) or value) case (byteIndex) 0: OUT <= value[31:24] ; 1: OUT <= value[23:16] ; 2: OUT <= value[15: 8] ; default: OUT <= value[ 7: 0] ;

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 20 Comparison of Styles l What will be the difference between the hardware synthesized from the simplified and sophisticated versions of the Data Converter code given in class?

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 21 Today’s Lecture l Data Converter Example l Review of the LC3 Instruction Set

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 22 ISA of LC3: General Info l 16-bit wide » Each word is 2-bytes wide » The memory space has 2 16 words l 8 general purpose registers l Data type: 2-complement integers l 15 instructions l Status registers: updated w/ registers » NZP

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 23 Instruction Format l Opcode » IR[15:12] l Addressing mode » Immediate (sign extension) » Register » Memory: PC relative » Memory: indirect » Memory: base+offset

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 24 ALU Operation Instructions l Also called “Operate” Instructions l AND » AND DR, SR1, SR2 (DR ← SR1 & SR2) » AND DR, SR1, Imm (DR ← SR1 & Imm) l ADD » ADD DR, SR1, SR2 (DR ← SR1 + SR2) » ADD DR, SR1, Imm (DR ← SR1 + Imm) l NOT » NOT DR, SR1 (DR ← ~SR1)

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 25 Operate Instructions l ADD l AND l NOT DR SR100 SR2 0 1 DR SR100 SR DR SR11 imm50 1 DR SR11 imm DR SR

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 26 Control Instructions l Branch » BRx Offset (PC ← PC+Offset) if any one of the specified flags is true » …where “x” is one or more Flags: (set based on the result of the last operation) –N - Negative –Z - Zero –P - Positive » Variations: » ==0 (BRZ) » !=0 (BRNP) » >0 (BRP) » >=0 (BRZP) » <0 (BRN) » <=0 (BRNZ) » Unconditional jump (BRNZP or simply BR) » Unconditional NOT jump (BRNONE)

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 27 Control Instructions l Jump » JMP BaseR (PC ← BaseR) l Ignore the other instructions for now » JSR, JSRR, RET, RTI, TRAP

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 28 Control Instructions l BR l JMP l JSR l JSRR l RET l RTI l TRAP 0 0 NZP PCoffset BaseR BaseR PCoffset Trapvect8

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 29 Data Movement Instructions l Load/Store (PC relative addressing mode) » LD DR, Offset (DR ← MEM[PC+Offset]) » ST SR, Offset (MEM[PC+Offset] ← SR) l Load/Store Register (Base+Offset addressing mode) » LDR DR, BaseR, Offset (DR ← MEM[BaseR+Offset]) » STR SR, BaseR, Offset (MEM[BaseR+Offset] ← SR)

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 30 Data Movement Instructions l Load/Store Indirect (indirect addressing mode) » LDI DR, Offset (DR ← MEM[MEM[PC+Offset]]) » STI SR, Offset (MEM[MEM[PC+Offset]] ← SR) l Load Effective Address » LEA DR, Offset (DR ← PC+Offset)

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 31 Data Movement Instructions l LD: l LDR: l LDI: l LEA: l ST: l STR: l STI: DR BaseR Offset DR PCoffset91 0 DR PCoffset DR PCoffset SR PCoffset SR PCoffset SR BaseR Offset6

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 32 Compile & Execute This Code 16’h01FFand r0, r0, #0; 16’h0200add r0, r0, #7; 16’h0201 and r1, r1, #0; 16’h0202 add r1, r1, #5; 16’h0203 add r0, r0,#-1; 16’h0204 brp #-3; 16’h0205 st r1, #2; 16’h0206 lea r6, #4; 16’h0207 jmp r6; 16’h0208 var1:; (0000) 16’h0209 var2:; (0000) 16’h020A var3:; (0000) 16’h020B …

Spring 20067W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406Slide 33 Finish Executing the Code 16’h0208 var1:; (0000) 16’h0209 var2:; (0000) 16’h020A var3:; (0000) 16’h020B ld r2, #-4; (25FC) 16’h020C add r2, r2, #1; (14A1) 16’h020D str r2, r6, #-2; (75BE) 16’h020E str r6, r6, #-1 ; (7DBF) 16’h020F ldi r3, #-6; (A7FA) 16’h0210 brnzp #-1; (0FFF)