Page 1EL/CCUT T.-C. Huang Nov TCH CCUT Introduction to IC Design Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech /11/24
Page 2EL/CCUT T.-C. Huang Nov TCH CCUT Clocking Strategies 1.Clocked System 2.Latch and Registers 3.System Timing (Constraint) 4.Single-Phase Memory 5.Phase Locked Loop Clock Techniques 6.Metastability and Synchronization Failure 7.Single-Phase Logic Structure 8.Two-Phase Clocking 9.Two-Phase Memory Structure 10.Two-Phase Logic Structures 11.Four-Phase Clocking 12.Four-Phase Memory Structures 13.Four-Phase Logic Structures 14.Clock Distribution
Page 3EL/CCUT T.-C. Huang Nov TCH CCUT Clocking Strategies Huffman Model for a Finite State Machine (review) QD QD QD QD Combinational Circuit PI: Primary Inputs PPI: Pseudo PI PO: Primary Outputs PPO: Pseudo PO Clk M L N M
Page 4EL/CCUT T.-C. Huang Nov TCH CCUT Clocking Strategies Basic Loop Timing Constraints (review) QD QD QD QD C T setup hold
Page 5EL/CCUT T.-C. Huang Nov TCH CCUT Clocking Strategies Timing Constraints Considering Jitter & Skew (review) QD QD QD QD Clk Jitter Skew
Page 6EL/CCUT T.-C. Huang Nov TCH CCUT Latch Function (review) 1.Level-Enabled (E, EN, Enable, Clk) 2.Function:Q=D if E=1 No Change if E=0 DQ EN High-Level Enabled DQ EN Low-Level Enabled
Page 7EL/CCUT T.-C. Huang Nov TCH CCUT RS Latch (review) S R S R S R
Page 8EL/CCUT T.-C. Huang Nov TCH CCUT D Latch (review) 1 0 D EN Static: 0 1 D EN Dynamic: DQ Weak-Static:
Page 9EL/CCUT T.-C. Huang Nov TCH CCUT Multiplex (review) A B 0 1 A B C A B C Z C
Page 10EL/CCUT T.-C. Huang Nov TCH CCUT Transparent Output DQ EN DQ t PG
Page 11EL/CCUT T.-C. Huang Nov TCH CCUT Flip-Flops Function (review) 1.Edge-Triggered 2.Usually consisted of a low- and a high latches DQ EN DQ DQ DQ D Q D Q
Page 12EL/CCUT T.-C. Huang Nov TCH CCUT Flip-Flops without Transparency DQ EN DQ Fully self-constrained!
Page 13EL/CCUT T.-C. Huang Nov TCH CCUT Flip-Flops A static positive-edge D Flip-flop (Vdd>2Vt) (review) D Clk Q
Page 14EL/CCUT T.-C. Huang Nov TCH CCUT Synchronous v.s. Asynchronous Control Settable, Resettable, etc. SynchronousAsynchronous Structural Behavioral Control Q No Clk in the path to Q Control Q With Clk in the path to Q Clk or posedge Control) if(Control) Controlled_state; else Clocked_circuit; Clk) if(Control) Controlled_state; else Clocked_circuit;
Page 15EL/CCUT T.-C. Huang Nov TCH CCUT Clock Buffering Clock Tree with a branch Degree of 3 or 4 (~ 2.718) without consideration of route A single large buffer:
Page 16EL/CCUT T.-C. Huang Nov TCH CCUT H-Tree
Page 17EL/CCUT T.-C. Huang Nov TCH CCUT Contra-data Direction Clock D Q D Q D Q D Q D Q D Q R C Data D Q D Q D Q D Q D Q D Q R C Generally,
Page 18EL/CCUT T.-C. Huang Nov TCH CCUT Phase Lock Loop (PLL) Phase Detector Charge Pump LPFVCO Frequency Divider U D 1.Skew Reduction; Synchronization 2.Frequency Multiplier 3.Data Recovery
Page 19EL/CCUT T.-C. Huang Nov TCH CCUT A Typical VCO Current mirror 180-degree oscillator Vc fofo
Page 20EL/CCUT T.-C. Huang Nov TCH CCUT VCDL Voltage Control Delay Line Vc toto titi
Page 21EL/CCUT T.-C. Huang Nov TCH CCUT PLL Clock Generator Clock PLL D Q D Q
Page 22EL/CCUT T.-C. Huang Nov TCH CCUT PLLs Applied to Different Domains Skew (ps) Equivalent Distance (ps) Max Skew PLL1 PLL2 PLL3 CLK
Page 23EL/CCUT T.-C. Huang Nov TCH CCUT Metastability & Synchronization Failure Wanted Data Next Data Clock Setup Hold Wanted Data Next Data Wanted Data Next Data Wanted Data Next Data Logic Error!
Page 24EL/CCUT T.-C. Huang Nov TCH CCUT Skew-Tolerant Design 1.Reverse Order of Clocking for only scan 2.Skew-Tolerant Dynamic Circuit 3.Skew-Tolerant Domino 4.Clock Domain Ranging
Page 25EL/CCUT T.-C. Huang Nov TCH CCUT Single-Clock Complementary Phase Combinational Circuit L Combinational Circuit H DHDH QLQL DLDL QHQH XLXL XHXH TLTL THTH
Page 26EL/CCUT T.-C. Huang Nov TCH CCUT Single-Clock Complementary Phase Timing Diagram DLDL Clk DHDH
Page 27EL/CCUT T.-C. Huang Nov TCH CCUT Single-Clock Double Edge 1.Can slack the master clock only. 2. TLTL THTH QD QD QD QD Combinational Circuit
Page 28EL/CCUT T.-C. Huang Nov TCH CCUT Single-Clock Complementary Phase Latch System Combinational Circuit L Combinational Circuit H DHDH QLQL DLDL QHQH XLXL XHXH TLTL THTH Data Transparency!
Page 29EL/CCUT T.-C. Huang Nov TCH CCUT Single-Clock 2 Phase Combinational Circuit 1 Combinational Circuit 2 D2D2 Q2Q2 X2X2 X2X2 Q1Q1 D1D1
Page 30EL/CCUT T.-C. Huang Nov TCH CCUT Comparison of some DFF’s D Clk Q D 1:1 static dynamic #clock #phase 1 1 C 2 2 local load contention Vt degrading
Page 31EL/CCUT T.-C. Huang Nov TCH CCUT N-Phase Clock Notations
Page 32EL/CCUT T.-C. Huang Nov TCH CCUT 4-Phase FF Precharge Redistribute Evaluate Precharge Redistribute Evaluate
Page 33EL/CCUT T.-C. Huang Nov TCH CCUT Johnson Counter
Page 34EL/CCUT T.-C. Huang Nov TCH CCUT Multiple Phase Clock Generator
Page 35EL/CCUT T.-C. Huang Nov TCH CCUT Clock Domain Programming Skew Frequency multiplicity Phase
Page 36EL/CCUT T.-C. Huang Nov TCH CCUT Clock Domain Interface Latch-base Bufer Leading Phase Logic Lagging Phase Logic Latch-base Bufer Lagging Phase Logic Leading Phase Logic with 1 cycle delay SIPO Integer-Times Frequency Low--Frequency Circuit PISO Low-Frequency Circiut Integer-Times Frequency PLL Data Recovery Skewed or Remote Clock recovered But delayed
Page 37EL/CCUT T.-C. Huang Nov TCH CCUT Clock Gating Problem D3Q3 D1Q1 D2 Q2 Discussed in advanced topic and should be careful!
Page 38EL/CCUT T.-C. Huang Nov TCH CCUT A Simple Clock Gating Condiction 1.Single Clock, Single Phase, Positive-Edge Trigger for Ungated and Gated Circuits 2.Gating Signal can be synchronized at negative edges and generated from the complementary clock domain. 3.Assme Clock Gating delay: t CG