Fast Lookup for Dynamic Packet Filtering in FPGA REPORTER: HSUAN-JU LI 2014/09/18 Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on (DDECS), rd International Conference on, April (2014) Luka´s Kekely, Martin ˇ Zˇ adn ´ ´ık, Jiˇr´ı Matousek, Jan Ko ˇ ˇrenek

Outline Introduction Related Work Design And Architecture Evaluation And Results Conclusion 2

Outline Introduction Related Work Design And Architecture Evaluation And Results Conclusion 3

Introduction Software applications of safety- and security-critical embedded systems are often divided into several self-contained functions. Between individual system partitions and functions. We use segregation to confine error propagation. Soft processors are one order of magnitude slower in terms of operating frequency than hard-wired devices. 4

Introduction(cont.) Current FPGA families provide wide and fast memory attachments mostly implemented as hard macros that are faster than configurable logic. There is a performance gap between soft processors and the memory attachment. Propose an architecture combines : The specific needs of partitioned software. The flexibility of reconfigurable hardware. 5

Introduction(cont.) Multiple self-contained systems on a single platform FPGA Shares available memory bandwidth among the systems In a predictable and scalable way. The main building blocks of the proposed architecture Secure bus bridges that are used to form a segregated hierarchy of memory busses. 6

Introduction(cont.) With secure bus bridges, it is possible to use soft processors for safety and security-critical functions. To reach high assurance levels with far less effort. 7

Outline Introduction Related Work Design And Architecture Evaluation And Results Conclusion 8

Related Work Cuckoo hash function h(x) h’(x) x = {a, b, c} 9 h(a)h(b)h(c) h’(b)h’(c)h’(a) h(a)h(b)h(c) h’(b)h’(c)h’(a) h(6) = 6 mod 11 = 6 h’(6) = floor(6/11) mod 11 = 0 x ={20, 50, 53,75}

Outline Introduction Related Work Design And Architecture Evaluation And Results Conclusion 10

Design And Architecture A. Lookup engine interface and functionality B. Cuckoo hash lookup engine C. Binary search tree lookup engine 11

Design And Architecture(cont.) A. Lookup engine interface and functionality B. Cuckoo hash lookup engine C. Binary search tree lookup engine 12

Design And Architecture(cont.) Lookup engine interface and functionality 13 Lookup Engine Key Width Data Width Maximum Capacity Representation in bits Interface

Design And Architecture(cont.) Lookup engine interface and functionality Lookup procedure 3 basic groups: Input Output Configuration 14

Design And Architecture(cont.) Lookup engine interface and functionality Lookup procedure 3 basic groups: 15 Lookup Engine Input keysLookup results Routing decision Key identification Arbitrary Data1 bit information Found Invalid (Outputs) Configuration (Every Clock Cycle)

Design And Architecture(cont.) A. Lookup engine interface and functionality B. Cuckoo hash lookup engine C. Binary search tree lookup engine 16

Design And Architecture(cont.) Cuckoo hash lookup engine 17

Design And Architecture(cont.) Cuckoo hash lookup engine 18 Parallel computing CRC implementation

Design And Architecture(cont.) Cuckoo hash lookup engine 19 Reading records Key valuedata Record Records from hash tables in memory or outside register

Design And Architecture(cont.) Cuckoo hash lookup engine 20 Compared for equality At most one comparison successful Data associated with matching key and set flag

Design And Architecture(cont.) Cuckoo hash lookup engine 21 Update key set based on requests received

Design And Architecture(cont.) Cuckoo hash lookup engine 22 Controller can evict records from hash tables on-the-fly preserving the set of active keys Reconfiguration cycle

Design And Architecture(cont.) Cuckoo hash lookup engine 23 C cuckoo = d x t + 1 d – The number of used hash tables(hash functions) t – The size of individual table 1 – Additional reconfiguration register

Design And Architecture(cont.) A. Lookup engine interface and functionality B. Cuckoo hash lookup engine C. Binary search tree lookup engine 24

Design And Architecture(cont.) Binary search tree lookup engine 25 Tree level (pipeline stage) Piece of memory Stage Address of a node Searched Key Comparator

Design And Architecture(cont.) Binary search tree lookup engine 26 Containing associated data to the key Piece of memory Stage Address of a node Searched Key Comparator

Design And Architecture(cont.) Binary search tree lookup engine 27 Atomic operations Piece of memory Stage Address of a node Searched Key Comparator Result corrected according to a register

28 The capacity of the BST based engine can be configured by the number of BST levels l. C bst = 2 l - 1 Design And Architecture(cont.) Binary search tree lookup engine

Design And Architecture(cont.) A. Lookup engine interface and functionality B. Cuckoo hash lookup engine C. Binary search tree lookup engine D. Top-level lookup engine 29

30 Design And Architecture(cont.) Top-level lookup engine Both Cuckoo and BST engine in parallel Both results are stored in FIFOs Cuckoo engineBST engine Stash FIFO

C total = d×t+1+s. d and t of the cuckoo hash and the stash size s 31 Design And Architecture(cont.) Top-level lookup engine The maximum capacity of the cuckoo hash with stash lookup engine can be defined:

Outline Introduction Related Work Design And Architecture Evaluation And Results Conclusion 32

Evaluation And Results Memory utilization can be computed in two basic ways: U cuckoo = (n−m)/C cuckoo U total = n/C total n: Total number of successfully inserted keys before the memory became full m: The number of keys that resides in the stash Stash can be always filled up to 100% of its capacity It can always put m = s The values of n must be acquired from the test runs 33

Evaluation And Results Evaluate the relation between achievable memory utilization of cuckoo hash and the used sizes of stash for different parameters. The memory utilization plotted in the graphs is U cuckoo and the size of the stash (s) is plotted as a portion of t. 34

Evaluation And Results(cont.) 35

Evaluation And Results(cont.) 36

Evaluation And Results(cont.) 37

Evaluation And Results(cont.) 38

Outline Introduction Related Work Design And Architecture Evaluation And Results Conclusion 39

Conclusion The proposed architecture leverages the combination of the cuckoo hash engine with BST engine with a focus on parallel implementation in FPGA. 40

THANK YOU 41