EE 5340 Semiconductor Device Theory Lecture 6 - Fall 2009 Professor Ronald L. Carter
L 06 Sept 10 Second Assignment Please print and bring to class a signed copy of the document appearing at 2
L 06 Sept 103 Approximate func- tion for extrinsic, compensated n-Si 1 Param.AsP min max N ref 9.68e169.20e16 N d > N a n-type n o = N d - N a = n o q n N I = N d + N a N As > N P As par N P > N As As par p o = n i 2 /n o
L 06 Sept 104 Approximate func- tion for extrinsic, compensated p-Si 1 ParameterB min 44.9 max N ref 2.23e17 N a > N d p-type p o = N a - N d = p o q p N I = N d + N a N a = N B B par n o = n i 2 /p o
L 06 Sept 105 Net silicon extr resistivity (cont.) Since = (nq n + pq p ) -1, and n > p, ( = q /m*) we have p > n, for the same N I Note that since 1.6(high conc.) < p / n < 3(low conc.), so 1.6(high conc.) < n / p < 3(low conc.)
L 06 Sept 106 Net silicon (com- pensated) res. For an n-type (n >> p) compensated semiconductor, = (nq n ) -1 But now n = N N d - N a, and the mobility must be considered to be determined by the total ionized impurity scattering N d + N a N I Consequently, a good estimate is = (nq n ) -1 = [Nq n (N I )] -1
Figure 1.16 (p. 31 M&K) Electron and hole mobilities in silicon at 300 K as functions of the total dopant concentration. The values plotted are the results of curve fitting measurements from several sources. The mobility curves can be generated using Equation with the following values of the parameters [3] (see table on next slide). L 06 Sept 107
8 Summary The concept of mobility introduced as a response function to the electric field in establishing a drift current Resistivity and conductivity defined (N d,N a,T) model equation developed Resistivity models developed for extrinsic and compensated materials
L 06 Sept 109 Equipartition theorem The thermodynamic energy per degree of freedom is kT/2 Consequently,
L 06 Sept 1010 Carrier velocity saturation 1 The mobility relationship v = E is limited to “low” fields v < v th = (3kT/m*) 1/2 defines “low” v = o E[1+(E/E c ) ] -1/ , o = v 1 /E c for Si parameter electrons holes v 1 (cm/s) 1.53E9 T E8 T E c (V/cm) 1.01 T T 1.68 2.57E-2 T T 0.17
L 06 Sept 1011 Carrier velocity 2 carrier velocity vs E for Si, Ge, and GaAs (after Sze 2 )
L 06 Sept 1012 Carrier velocity saturation (cont.) At 300K, for electrons, o = v 1 /E c = 1.53E9(300) /1.01(300) 1.55 = 1504 cm 2 /V-s, the low-field mobility The maximum velocity (300K) is v sat = o E c = v 1 = 1.53E9 (300) = 1.07E7 cm/s
L 06 Sept 1013 Diffusion of Carriers (cont.)
L 06 Sept 1014 Diffusion of carriers In a gradient of electrons or holes, p and n are not zero Diffusion current, J = J p + J n (note D p and D n are diffusion coefficients)
L 06 Sept 1015 Diffusion of carriers (cont.) Note ( p) x has the magnitude of dp/dx and points in the direction of increasing p (uphill) The diffusion current points in the direction of decreasing p or n (downhill) and hence the - sign in the definition of J p and the + sign in the definition of J n
L 06 Sept 1016 Current density components
L 06 Sept 1017 Total current density
L 06 Sept 1018 Doping gradient induced E-field If N = N d -N a = N(x), then so is E f -E fi Define = (E f -E fi )/q = (kT/q)ln(n o /n i ) For equilibrium, E fi = constant, but for dN/dx not equal to zero, E x = -d /dx =- [d(E f -E fi )/dx](kT/q) = -(kT/q) d[ln(n o /n i )]/dx = -(kT/q) (1/n o )[dn o /dx] = -(kT/q) (1/N)[dN/dx], N > 0
L 06 Sept 1019 Induced E-field (continued) Let V t = kT/q, then since n o p o = n i 2 gives n o /n i = n i /p o E x = - V t d[ln(n o /n i )]/dx = - V t d[ln(n i /p o )]/dx = - V t d[ln(n i /|N|)]/dx, N = -N a < 0 E x = - V t (-1/p o )dp o /dx = V t (1/p o )dp o /dx = V t (1/N a )dN a /dx
L 06 Sept 1020 The Einstein relationship For E x = - V t (1/n o )dn o /dx, and J n,x = nq n E x + qD n (dn/dx) = 0 This requires that nq n [V t (1/n)dn/dx] = qD n (dn/dx) Which is satisfied if
L 06 Sept 1021 Silicon Planar Process 1 M&K 1 Fig. 2.1 Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) oxide removal, (c) deposition of dopant atoms, (d) diffusion of dopant atoms into exposed regions of silicon.
L 06 Sept 1022 LOCOS Process 1 1 Fig 2.26 LOCal Oxidation of Silicon (LOCOS). (a) Defined pattern consisting of stress-relief oxide and Si 3 N 4 where further oxidation is not desired, (b) thick oxide layer grown over the bare silicon region, (c) stress- relief oxide and Si 3 N 4 removed by etching, (d) scanning electron micrograph (5000 X) showing LOCOS- processed wafer at (b).
L 06 Sept 1023 Al Interconnects 1 1 Figure 2.33 (p. 104) A thin layer of aluminum can be used to connect various doped regions of a semiconductor device. 1
L 06 Sept 1024 Ion Implantation 1 1 Figure 2.15 (p. 80) In ion implantation, a beam of high-energy ions strikes selected regions of the semiconductor surface, penetrating into these exposed regions.
L 06 Sept 1025 Phosphorous implant Range (M&K 1 Figure 2.17) Projected range R p and its standard devia- tion R p for implantation of phosphorus into Si, SiO 2, Si 3 N 4, and Al [M&K ref 11].
L 06 Sept 1026 Implant and Diffusion Profiles Figure Complementary- error-function and Gaussian distribu- tions; the vertical axis is normalized to the peak con- centration Cs, while the horizon- tal axis is normal- ized to the char- acteristic length
L 06 Sept 1027 Diffused or Implanted IC Resistor (Fig )
L 06 Sept 1028 An IC Resistor with L = 8W (M&K) 1
L 06 Sept 1029 Typical IC doping profile (M&K Fig )
L 06 Sept 1030 Mobilities**
L 06 Sept 1031 IC Resistor Conductance
L 06 Sept 1032 An IC Resistor with N s = 8, R = 8R s (M&K) 1
L 06 Sept 1033 The effect of lateral diffusion (M&K 1 )
L 06 Sept 1034 A serpentine pattern IC Resistor (M&K 1 ) R = N S R S N C R S note: R C = 0.65 R S
L 06 Sept 1035 Band model review (approx. to scale) qm~4+Vqm~4+V EoEo E Fm E Fp E Fn EoEo EcEc EvEv E Fi q s,n q s ~ 4 + V EoEo EcEc EvEv E Fi q s,p metaln-type s/cp-type s/c q s ~ 4 + V
L 06 Sept 1036 Making contact be- tween metal & s/c Equate the E F in the metal and s/c materials far from the junction E o (the free level), must be continuous across the jctn. N.B.: q = 4.05 eV (Si), and q = q E c - E F EoEo EcEc EFEF E Fi EvEv q (electron affinity) qFqF qq (work function)
L 06 Sept 1037 Ideal metal to p-type barrier diode ( m < s ) E Fp EoEo EcEc EvEv E Fi q s,p qsqs p-type s/c qmqm E Fm metal q Bn qV bi q p <0 No disc in E o E x =0 in metal ==> E o flat Bn = m - s = elec mtl to s/c barr V bi = Bp - s,p = hole s/c to mtl barr Depl reg
L 06 Sept 1038 Ideal metal to n-type barrier diode ( m > s,V a =0) E Fn EoEo EcEc EvEv E Fi q s,n qsqs n-type s/c qmqm E Fm metal q Bn qV bi q’nq’n No disc in E o E x =0 in metal ==> E o flat Bn = m - s = elec mtl to s/c barr V bi = Bn - n = m - s elect s/c to mtl barr Depl reg
L 06 Sept 1039 Ideal metal to n-type Schottky (V a >0) qV a = E fn - E fm Barrier for electrons from sc to m reduced to q(V bi -V a ) q Bn the same DR decr E Fn EoEo EcEc EvEv E Fi q s,n qsqs n-type s/c qmqm E Fm metal q Bn q(V bi -V a ) q’nq’n Depl reg
L 06 Sept 1040 References 1 Device Electronics for Integrated Circuits, 2 ed., by Muller and Kamins, Wiley, New York, See Semiconductor Device Fundamentals, by Pierret, Addison-Wesley, 1996, for another treatment of the model. 2 Physics of Semiconductor Devices, by S. M. Sze, Wiley, New York, Semiconductor Physics & Devices, 2nd ed., by Neamen, Irwin, Chicago, 1997.