SEU Hardening Incorporating Extreme Low Power Bitcell Design (SHIELD) Ariel Pescovsky and Oron Chertkow Supervisors: Prof. Alexander Fish Dr. Alexander Belenky Mr. Lior Atias 1

Outline Radiation in Space SEU Mechanism Power Consumption Our Proposed Cell Simulation’s Results Physical Layout Conclusion

Radiation Sources IN SPACE: Solar Activity Galactic Cosmic Rays protons (90%), alpha particles (10-5%) and heavy ions Galactic Cosmic Rays High energy protons (85%), alpha particles (14%) and heavy ions (less than 1%) originated outside of our solar system. Van Allen Belts IN Earth’s Atmosphere: Secondary particles Mostly Hazardous for electronic devices are Neutrons. 3 3

Radiation Effect on Micro-electronics Two main mechanisms Direct Ionization (primary mechanism caused by heavy ions ) Indirect ionization

Particle Impact Modeling

Single Event Upset (SEU) in SRAM Qcrit – The maximal amount of collected charge that a node can withstand without causing an upset

Radiation at Earth’s Atmosphere

Power Consumption in SRAM 𝑃 𝑑𝑦𝑛𝑎𝑚𝑖𝑐 =𝑓∙ 𝐶 𝑒𝑓𝑓 ∙ 𝑉 𝐷𝐷 2 𝑃 𝑠𝑡𝑎𝑡𝑖𝑐 = 𝐼 𝑙𝑒𝑎𝑘𝑎𝑔𝑒 ∙ 𝑉 𝐷𝐷 SRAM array ~70% Solution – scaling the supply voltage

Qcrit Voltage Dependency Lowering supply voltage induce lower Qcrit values Qcrit = Cnode ∙Vnode

The Proposed Cell

The Proposed Cell Hold State Write Process

Particle impact at Q1 ‘1’ -> ‘0’ 1 1

Particle impact at Q1 ‘0’ -> ‘1’ 1

Particle impact at Q2 ‘0’ -> ‘1’ 1

Write-Impact-Read Sequence New graph wight

SEU Simulation Results SHIELD 6T DICE Quarto Robust Q1: 1-> 0 [fC] Over 1pC 2.2 Q1: 0-> 1 [fC] 5.6 3.7 Q2: 1-> 0 [fC] NP* - 2.5 Q2: 0-> 1 [fC] Final Qcrit [fC] NP*- Not Possible (Junction is not in reverse bias)

Power Simulation Results   leakage current [pA] Static Power [pW] SHIELD 25.37 17.759 6T 38.97 27.279 DICE 41.93 29.351 12T 1,444 1,367 Quatro 52.5 49.456

Leakage Currents Comparison

Physical Layout (65nm) Only 2.07 times bigger then the standard 6T bitcell 4.3 µm 0.93 µm 6T Over all area: 4 µ𝒎 𝟐

SHIELD vs. Triple Modular Redundancy Three 6T SRAM bitcells

Triple Modular Redundancy

Project Achievements Qcrit improvement: more than 455 X Static Power reduction: more than 2 X Low voltage functionality at 700mV Small layout design A paper issued to IEEE SOI-3D-Subthreshold microelectronics conference.

Any Questions?

YouTube Link https://www.youtube.com/watch?v=jLiHu3Y055U&feature=youtu.be