Mid3 Revision 3 Prof. Sin-Min Lee Department of Computer Science

Flip Flops and Characteristic Tables Q(t+1) = D Q(t+1)= K’Q(t) + JQ’(t) Q(t+1)= T’Q(t) + TQ’(t) = T  Q(t)

Example Implement a JK flip-flop using a D flip-flop and primitive gates.

Example Implement a JK flip-flop using a D flip-flop and primitive gates.

Example Implement a JK flip-flop using a D flip-flop and primitive gates.

Example Implement a JK flip-flop using a D flip-flop and primitive gates. JKQQ+D

Example Implement a JK flip-flop using a D flip-flop and primitive gates. JKQQ+D

Example Implement a JK flip-flop using a D flip-flop and primitive gates. JKQQ+D

Example Implement a JK flip-flop using a D flip-flop and primitive gates. JKQQ+D

Example Implement a JK flip-flop using a D flip-flop and primitive gates. JKQQ+D J K Q

Example Implement a JK flip-flop using a D flip-flop and primitive gates. JKQQ+D J K Q D = Q K’ + Q’ J

D Q¹ Q’ T Q° Clock I Y

D Q¹ Q’ T Q° Clock I Y I Q¹ Q° Y Start

D Q¹ Q’ T Q° Clock I Y I Q¹ Q° Y Clock Cycle 1 Note: Q outputs are dependant on the state of inputs present on the previous cycle.

D Q¹ Q’ T Q° Clock I Y I Q¹ Q° Y Clock Cycle 2 Note: Q outputs are dependant on the state of inputs present on the previous cycle.

D Q¹ Q’ T Q° Clock I Y I Q¹ Q° Y Clock Cycle 3 Note: Q outputs are dependant on the state of inputs present on the previous cycle.

D Q¹ Q’ T Q° Clock I Y I Q¹ Q° Y Clock Cycle 4 Note: Q outputs are dependant on the state of inputs present on the previous cycle.

D Q¹ Q’ T Q° Clock I Y I Q¹ Q° Y Clock Cycle 5 Note: Q outputs are dependant on the state of inputs present on the previous cycle.

D Q¹ Q’ T Q° Clock I Y I Q¹ Q° Y Clock Cycle 6 Note: Q outputs are dependant on the state of inputs present on the previous cycle.

D Q¹ Q’ T Q° Clock I Y I Q¹ Q° Y Clock Cycle 7 Note: Q outputs are dependant on the state of inputs present on the previous cycle.

D Q¹ Q’ T Q° Clock I Y I Q¹ Q° Y Clock Cycle 8 Note: Q outputs are dependant on the state of inputs present on the previous cycle.

Some commonly used components Decoders: n inputs, 2 n outputs. –the inputs are used to select which output is turned on. At any time exactly one output is on. Multiplexors: 2 n inputs, n selection bits, 1 output. –the selection bits determine which input will become the output. Adder: 2n inputs, 2n outputs. –Computer Arithmetic.

Multiplexer “ Selects ” binary information from one of many input lines and directs it to a single output line. Also known as the “ selector ” circuit, Selection is controlled by a particular set of inputs lines whose # depends on the # of the data input lines. For a 2 n -to-1 multiplexer, there are 2 n data input lines and n selection lines whose bit combination determines which input is selected.

MUX 2 n Data Inputs Data Output Input Select n Enable

Remember the 2 – 4 Decoder? S1S1 S0S0 Sel(3) Sel(2) Sel(1) Sel(0) Mutually Exclusive (Only one O/P asserted at any time

4 to 1 MUX Decoder Control DataFlow D3:D0 4 Sel(3:0) 4 S1:S0 2 Dout

4-to-1 MUX (Gate level) Three of these signal inputs will always be 0. The other will depend on the data value selected Control Section

Until now, we have examined single-bit data selected by a MUX. What if we want to select m-bit data/words?  Combine MUX blocks in parallel with common select and enable signals Example: Construct a logic circuit that selects between 2 sets of 4-bit inputs (see next slide for solution). Multiplexer (cont.)

Example: Quad 2-to-1 MUX Uses four 4-to-1 MUXs with common select (S) and enable (E). Select line chooses between A i ’ s and B i ’ s. The selected four- wire digital signal is sent to the Y i ’ s Enable line turns MUX on and off (E=1 is on).

Implementing Boolean functions with Multiplexers Any Boolean function of n variables can be implemented using a 2 n-1 -to-1 multiplexer. A MUX is basically a decoder with outputs ORed together, hence this isn ’ t surprising. The SELECT signals generate the minterms of the function. The data inputs identify which minterms are to be combined with an OR.

Example F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7) 2 2 -to-1 MUXThere are n=3 inputs, thus we need a 2 2 -to-1 MUX The first n-1 (=2) inputs serve as the selection linesThe first n-1 (=2) inputs serve as the selection lines

Efficient Method for implementing Boolean functions For an n-variable function (e.g., f(A,B,C,D)): –Need a 2 n-1 line MUX with n-1 select lines. –Enumerate function as a truth table with consistent ordering of variables (e.g., A,B,C,D) –Attach the most significant n-1 variables to the n-1 select lines (e.g., A,B,C) –Examine pairs of adjacent rows (only the least significant variable differs, e.g., D=0 and D=1). –Determine whether the function output for the (A,B,C,0) and (A,B,C,1) combination is (0,0), (0,1), (1,0), or (1,1). –Attach 0, D, D ’, or 1 to the data input corresponding to (A,B,C) respectively.

Another Example Consider F(A,B,C) =  m(1,3,5,6). We can implement this function using a 4-to-1 MUX as follows. The index is ABC. Apply A and B to the S 1 and S 0 selection inputs of the MUX (A is most sig, S 1 is most sig.) Enumerate function in a truth table.

MUX Example (cont.) ABCF When A=B=0, F=C When A=0, B=1, F=C When A=1, B=0, F=C When A=B=1, F=C’

MUX implementation of F(A,B,C) =  m(1,3,5,6) A B C C C C’ F

2 Input Multiplexor Inputs: I 0 and I 1 Selector: S Output: O If S is a 0: O=I 0 If S is a 1: O=I 1 Mux I0I0 I1I1 O S

2-Mux Logic Design I1I1 I0I0 S O I 0 && !S I 1 && S

4 Input Multiplexor Inputs: I 0 I 1 I 2 I 3 Selectors: S 0 S 1 Output: O Mux I0I0 I2I2 O S0S0 S0S0 S1S1 O 00I0I0 01I1I1 10I2I2 11I3I3 I1I1 I3I3 S1S1

One Possible 4-Mux 2-Decoder I0I0 I1I1 I2I2 I3I3 S0S0 S1S1 O

Adder We want to build a box that can add two 32 bit numbers. –Assume 2s complement representation We can start by building a 1 bit adder.

Addition We need to build a 1 bit adder –compute binary addition of 2 bits. We already know that the result is 2 bits. ABO0O0 O1O A + B O 0 O 1 This is addition!

One Implementation A B O0O0 !A B A !B O1O1 A && B (!A && B) || (A && !B)

Binary addition and our adder What we really want is something that can be used to implement the binary addition algorithm. –O 0 is the carry –O 1 is the sum Carry

What about the second column? We are adding 3 bits –new bit is the carry from the first column. –The output is still 2 bits, a sum and a carry Carry

Truth Table for Addition ABCarry In Carry Out Sum

Steps in Handling a Page Fault

Multiprogramming with Fixed Partitions Divide memory into n (possible unequal) partitions. Problem: –Fragmentation Free Space 0k 4k 16k 64k 128k

Fixed Partitions Legend Free Space 0k 4k 16k 64k 128k Internal fragmentation (cannot be reallocated)

Storage Placement Strategies Every placement strategy has its own problem –Best fit Creates small holes that cant be used –Worst Fit Gets rid of large holes making it difficult to run large programs –First Fit Creates average size holes

Locality of Reference Most memory references confined to small region Well-written program in small loop, procedure or function Data likely in array and variables stored together Working set –Number of pages sufficient to run program normally, i.e., satisfy locality of a particular program

Page Replacement Algorithms Page fault - page is not in memory and must be loaded from disk Algorithms to manage swapping –First-In, First-Out FIFO – Belady’s Anomaly –Least Recently Used LRU –Least Frequently Used LFU –Not Used Recently NUR Referenced bit, Modified (dirty) bit –Second Chance Replacement algorithms Thrashing –too many page faults affect system performance

How Bad Is Fragmentation? Statistical arguments - Random sizes First-fit Given N allocated blocks 0.5  N blocks will be lost because of fragmentation Known as 50% RULE

Solve Fragmentation w. Compaction MonitorJob 3 Free Job 5Job 6Job 7Job 8 5 MonitorJob 3 Free Job 5Job 6Job 7Job 8 6 MonitorJob 3 Free Job 5Job 6Job 7Job 8 7 MonitorJob 3 Free Job 5Job 6Job 7Job 8 8 MonitorJob 3 Free Job 5Job 6Job 7Job 8 9

Placement Policy Determines where in real memory a process piece is to reside Important in a segmentation system Paging or combined paging with segmentation hardware performs address translation

Replacement Policy Placement Policy –Which page is replaced? –Page removed should be the page least likely to be referenced in the near future –Most policies predict the future behavior on the basis of past behavior

Replacement Policy Frame Locking –If frame is locked, it may not be replaced –Kernel of the operating system –Control structures –I/O buffers –Associate a lock bit with each frame

Basic Replacement Algorithms Optimal policy –Selects for replacement that page for which the time to the next reference is the longest –Impossible to have perfect knowledge of future events

Basic Replacement Algorithms Least Recently Used (LRU) –Replaces the page that has not been referenced for the longest time –By the principle of locality, this should be the page least likely to be referenced in the near future –Each page could be tagged with the time of last reference. This would require a great deal of overhead.

Basic Replacement Algorithms First-in, first-out (FIFO) –Treats page frames allocated to a process as a circular buffer –Pages are removed in round-robin style –Simplest replacement policy to implement –Page that has been in memory the longest is replaced –These pages may be needed again very soon

Basic Replacement Algorithms Clock Policy –Additional bit called a use bit –When a page is first loaded in memory, the use bit is set to 1 –When the page is referenced, the use bit is set to 1 –When it is time to replace a page, the first frame encountered with the use bit set to 0 is replaced. –During the search for replacement, each use bit set to 1 is changed to 0

Parallel Organizations - SISD

Parallel Organizations - SIMD

Parallel Organizations - MIMD Shared Memory

Parallel Organizations - MIMD Distributed Memory

Block Diagram of Tightly Coupled Multiprocessor

History Cray Research founded in Cray Computer founded in First product – Cray-1 (240,000,000 OpS). Seymour Cray personally invented vector register technology Cray-2 (1,200,000,000 OpS, a 5-fold increase from Cray 1). Seymour is credited with immersion-cooling technology Cray-3 used revolutionary new gallium arsenide integrated circuits for the traditional silicon ones 1996 Cray was bought by SGI In March 2000 the Cray Research name and business was sold by SGI to Tera Inc.

Menu Weather forecasting Explanation OverviewOverview picture DataData collection Sensors Data logginglogging The Grid SystemSystem WeatherWeather station Radiosonde Satellites Radar WeatherWeather ships Supercomputers Parallel ProcessingProcessing Software Pressing Weather forecasting on any slide will bring you back to this menu

During the last two decades the Met Office has used state-of-the-art supercomputers for numerical weather prediction and more recently, also for predictions of global climate. WeatherWeather forecasting This is a picture of a supercomputer