97.575 Project : GasP pipeline in asynchronous circuit Wilson Kwan M.A.Sc. Candidate Ottawa-Carleton Institute for Electrical & Computer Engineering (OCIECE)

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Presentation transcript:

Project : GasP pipeline in asynchronous circuit Wilson Kwan M.A.Sc. Candidate Ottawa-Carleton Institute for Electrical & Computer Engineering (OCIECE) Carleton University Ottawa, Canada April 17, 2002

Outline of the presentation What is GasP pipeline? Building blocks of GasP pipeline. Design Guidelines of GasP pipeline. Simulation result. Contributions. Milestones of the project.

What is GasP pipeline? GasP family of asynchronous circuit is a minimal control circuit for the pipeline. GasP pipeline is composed of "Place" and "Path" circuits. "Place" circuit is designed to hold the source data. "Path" circuit is designed to control the flow of data between "Place" circuit. One control signal wire is used to communicate between the pipelines.

Building blocks of GasP pipeline Two inverters connected back to back as a data latch and keeper (Place circuit) NAND structure circuit is to collaborate the signals from previous place circuit and next place circuit (Path circuit)

Block Diagram of GasP pipeline 1 1 Source data 0

Design Guidelines of GasP pipeline. (I) - Each stage of GasP pipeline operates at the speed of a three-inverter ring oscillator. - The forward latency is long while the reverse latency is short. - Derive the transistor size formula, user can optimize the widths of the transistor and obtain the uniform transistor delay. - Write the scripts to automate the job of finding the optimal transistor widths for delay time.

Design Guidelines of GasP pipeline. (II) - To equalize the performance of each pipeline stage, all control circuits use the same number of logic gates, usually three or five, in every closed loop. - Even numbers of gate-delays of both forward and reverse latency. - Choose the shorter value for the uniform gate delay gives more speed at the cost of more area and more power.

Schematic Diagram for path circuit

Schematic Diagram for place circuit

Simulation result. Initial guess of the transistor sizes: “a” inverter : 2u/0.35u “z” inverter : 1u/0.35u Self-reset circuit : 9u/0.35u, 2u/0.35u : 50ps y pass transistor : 9u/0.35u : 150ps p pass transistor : 1.5u/0.35u : 25ps For the forward latency: Estimated delay is 115 ps. Further simulation are needed.

Contributions. GasP pipeline minimizes the structure of asynchronous pipeline control circuit. One control signal wire is used to communicate between two stages of pipeline. High performance and low power dissipation can be achieved by reducing the number of transistors in the control circuit.

Milestones of the project. Task DaysExpected completion Completion date Read GasP pipeline: A minimal FIFO control paper and related papers 4March 25, 2002 Transistor size and delay calculation 4March 29, 2002 April 4, 2002 Scripts to optimize the transistor width and delay 2April 20, 2002

Milestones of the project. Task DaysExpected completion Completion date Draw the schematic diagram in Cadence program 2April 16, 2002 Simulation and transistor size correction 16April 18, 2002 Design modification and Testing 8April 26, 2002

Reference 1) I.E. Sutherland, “Micropipeline,” Comm. ACM, vol. 32, no.6, pp , June ) I.E. Sutherland and Scott Fairbanks, “GasP: A Minimal FIFO Control”, ) J. Ebergan, “Squaring the FIFO in GasP,” Proc. of the Seventh International Symposium on Advanced Research in Asynchronous Circuit and Systems, )I.E. Sutherland, B. Sproull, and D. Harris, “Logic Effort: Designing Fast CMOS circuits. Morgan Kaufmann Publishers, Inc., 1999.