Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Advanced Computer Architecture Lecture 5 Slave bus agent ROM example I/O write port example

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Slave block diagram Decode Data Source Data Sink Tri State A C D Ack LS138LS244 Device

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Decoding Inputs –Address bus –Control bus Fully decoded: unique address/function found Implementation (LS138) –Two levels: address, control –Use output of first level to enable second

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Decoding block diagram LS138 A C Correct address Correct address and function First and second level may be reversed

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Decoding for I/O write to 0xf

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering ROM block diagram Decode Data Source Tri State A C D Ack LS138LS244 ROM

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering ROM example requirements Address range 0x00 – 0x0f, 16 words CPU executes read memory instructions Data of ROM (f, e, d, …, 2, 1, 0) One master: Breq = Bgnt No interrupts: Int = gnd

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering ROM system schematic

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering ROM memory schematic ?

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering ROM data files Program ROM contents

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering ROM timing CPU driving A, C ROM driving D

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering ROM timing, continued. CPU driving A, C ROM driving D

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Changes for RAM Address bus: same Control bus: same Decoding: must look for memory read and memory write Data bus: connected to both RAM data in and data out ACK: same

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering I/O write port block diagram DecodeTri State A C D Ack LS138LS244 Octal D’s Data Sink V

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering I/O write port requirements Port address 0x10 CPU executes I/O write instructions Data: 1, 2, 4, 8, 10, 20, 40, 80 One master: Breq = Bgnt No interrupts: Int = gnd

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering I/O write port system schematic

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Write port schematic ?

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Write port data files Program

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Write port timing Write 0x01 to Port 10Write 0x02 to Port 10

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Changes for I/O read Address bus: same Control bus: same Decoding: look for I/O read instruction Data bus: must drive with tri-state devices ACK: same

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering ROM memory schematic ?

Spring EE 437 Lillevik 437s06-l5 University of Portland School of Engineering Write port schematic ?