Trigger System LIU Zhen’an Inst. of High Energy Physics, Beijing Sep

Outline General Event Rate design rules trigger in data flow trigger block diagram MDC trigger TOF trigger EMC subsystem Global Trigger Present status and Outlook

General: Estimation of event rate Fig:Backgrounds rate vs beam current At BESII/BEPC Purpose of trigger system: to accept all interested events to rejects as much background as possible DAQ is sustainable With good design of MDC,TOF and EMC trigger, we estimate that total trigger rate = good event rate (~2000, L BEPCII = 1  cm -2 s -1 ) + bhabha rate (~800,to be pre-scaled) + cosmic event rate (<200,from 1500) + beam background rate (<2000,from 13MHz) = ~ 4000 Hz

General:design rules Pipeline processing must be used in trigger Multi-bunches(93 in the ring) small bunch spacing(8ns) =>Latch-process-decision mode not possible in 8ns) Latency of trigger signal necessary 3.2  s No dead time in trigger system Most recent technology will be used

General: trigger system in data flow Hardware trigger + software filter FEE signal splitted: trigger + FEE pipeline FEE pipeline clock 40MHz Level 1(L1): 3.2  s FEE Control Logic checks L1 with FEE pipeline clock L1 YES: moves pipeline buffer data L1 No : overwritten by new data BESIII FEE pipeline and Data flow Detector switch Level 1 FEE pipeline Readout buffer Farms Disk Time Reference 0 s 3.2  s Ev.Filter PowerPC

Block Diagram of BES III Trigger Global Trigger Logic 3.2  s TOF MDC EMC MU DISC Mu track DISC TrigSum Track Finder Etotal Energy Hit/Seg Count Track Seg. Finder DAQ RF TTC TC Sum L1P CLOCK Track Match Energy Balance Cluster Counting

Nswires 9008 N axial 4008 N stereo 5000 N layers 47 Nlaxial 19 Nlstereo 28 N pivot cells ax 92/116/224/320/320 N pivot cells st 48/72/160/192/224/256/288 N spcells/sector 32/16 MDC Trigger-Signals

MDC trigger schemes GLT TSF cards On FEE GTSF BLT PTD/TF Axial& stereo TRK CNT Scheme A(AX only): TSF + TF + TRKCNT Scheme B(AX+ST): TSF + GTSF +BLT+PTD+TRKCNT

TSF(Track Segment Finding) Pivot layer Ideal case: same cells,high Pt Ideal case: same cells,high Pt Real case simulation These data is used for TS Finding

TSF-Daughter Board Block Diagram 32 Track segment finding driver receiver 8 8 stretcher Programable delay (LVPECL) (LVPECL/ LVDS) 1-5 Inputs Outputs driver rec 8 Left Neighbour driver 8 Left Neighbour Test and Control 8 VME R/W Commands TSF Daughter Board FPGA 1-3

GTSF(TSF grouping) and BLT(Binary Link Track) BLT Algorithm 2to1 OUT Mem IN Mem Control Mem DAQ Mem O R g a t e From GTSF To GLT BLT Long track BLT Short track AX-AX: N=3 AX-ST: N=3 ST-ST: N=5 SPC: SL1-2:1/16 SL5-11:1/32

PTD/TF Long track: Reference layer SL11 SL7,SL4 and SL3 4 / 4 or 3 / 4 PTD/TF Short track: Reference layer SL7 SL4 and SL3 3 / 3 or 2/3 Momentum Discrimination(PTD)/TF) SL11 SL7 SL4 SL3

FORTRAN code MDC structure + hits Trigger scheme Tasks: Feasibility of trigger scheme Trigger efficiency study Wire in-efficiency influence study Backgrounds rejecting ability study Production of configuration data Track Segment Finding Track Finding/PTD MDC trigger simulation

Trigger efficiency vs Pt and wire efficiency Configuration: Pt > 120 MeV tracks with Pt>130MeV + Weff>95% TrigEff>95% tracks with Pt>130MeV + Weff>95% TrigEff>95% TSF:Ncomb=8 TSF:Ncomb=24

very good rejection of artificial cosmic rays 10cm away from vertax(100% when requires Nltrk_ptd>1) Rejection for beam backgd understudy. Result to be given after inputs from beam background simulation is avalable MDC background rejection

TOF Trigger 48 Leading Edge Disc Mean Timer Leading Edge Disc Leading Edge Disc Leading Edge Disc Mean Timer L 1i1i &(L 2i-1 or L 2i+1 ) TOF Trigger Master Trigger Timing Hit count and topology logic Disc. TOFE PMT 88TOFB 88TOFB Disc. 48 TOFE

EMC trigger Barrel: θ×φ=56×144 = 8064 Endcap: 120 、 120 、 120 、 96 、 96 、 96 、 84 、 84 、 84 =1800 Basic trigger unit( trigger cell): sum of 24 crystals outputs

EMC Simulation <20% difference acceptable Gain adjustment for each crystal+PD+PreAmp chain Trigger Cell should be at least 4X4 =16 crystals. 4X6=24 is taken

BESIII EMC trigger scheme Gain Adj. FEE 8ch sum

Track Matching scheme TOF Track Distribution BEMC Track Distribution EEMC Track Distribution Input Signals Delay Input Signals Delay Input Signals Delay Input Signals Delay Matched Track Count To Main Trigger Controller Barrel Track Match Eadcap Track Match From TOF Trigger From EEMC Trigger From MDC Trigger From BEMC Trigger

Global Trigger (GLT) TOF-T Reset To TRG Sub-system Trigger Conditions L1 Programmable Input Signal Delay Programmable Trigger Event Decision Programmable Pre-scale Trigger Controller Clock Processor RF Multi-Scaler CHK INIT BUSY Trigger EVT E-TYPE Trigger Signals Distribution To Electronics TDC EMC-T EEMC-T Inputs: sub-detector conditions Time adjustment trigger table Pre-scaling of some event types

Trigger conditions

Timing and handshaking with DAQ CLK L1 Tdead Tlife 3s3s BUSY CHK TRG#= ns GEVT Trigger pipeline clock f RF = MHz f f RF /12  40MHz Blocking of L1 of 3  s required by Electronics fro peak finding #TRG error checking with CHK signal

Trigger scheme is drafted and will be refined. Trigger simulation goes well, will go further with physics and backgrounds study Pipelined digital signal generator Designed for other module testing. Signal Sequence Programmable, signal length programmable Readback Check, TTL/LVDS high reliability Experiment Board for VME Module Design Base on FPGA, to be used for testing other VME module’s functionality Pipeline Clock Generater/Divider Experiment done VMS BUS Display Prototyped. Manual Controller in Circuit design Digital programmable signal delay module is under debugging. MDC TSF board is modeled in FPGA with 32 inputs, and simulated, will begin board design Present Status and Outlook(1)

Present Status and Outlook(2) Preliminary Design: Jul End 2002 Prototype of sub-system modules: Apr Dec.2003 Test system and software:Oct.2002-Mar.2005 Mass production: Oct.2003-Mar.2005 Sub-system test: Jan Sep.2005 System integration/test Oct.2005-Dec.2005 Cosmic-ray test:Jan.2006-May 2006 Test run: End 2006

Summary Hardware trigger + software filter(on PC farm) L1 latency: 3.2  s Pipeline clock: 40 MHz Monte Carlo simulation going well backgrounds, MDC, EMC trigger schemes studies Design scheme drafted Some modules designed Further/detailed designing undergoing Welcome collaboration domestic and abroad

Thanks!